OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
397,002 Commits 31 Branches 0 Tags 2.2 GiB
Commit Graph

2 Commits

Author SHA1 Message Date
Jay Foad 58de4b2053 [AMDGPU] Use pseudo instructions for readlane/writelane 
This reverts r227987 "R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2".

All the codegen changes are caused by the post-RA scheduler no longer
treating readlane/writelane as scheduling barriers due to having
unmodelled side effects. (The pseudos are hasSideEffects = 0, but the
real instructions are hasSideEffects = ? which TableGen conservatively
treats as 1.)

Differential Revision: https://reviews.llvm.org/D90401
 2020-10-29 16:00:53 +00:00
Matt Arsenault 60ba03e210 AMDGPU: Fix not marking new gfx10 SGPRs as CSRs 
llvm-svn: 361330
 2019-05-21 23:23:05 +00:00