2 Commits

Author	SHA1	Message	Date
Stefan Pintilie	cb0c034edc	[PowerPC] Fix issue where vsrq is given incorrect shift vector ... The new Power10 instruction vsrq was being given the wrong shift vector. The original code assumed that the shift would be found in bits 121 to 127. This is not correct. The shift is found in bits 57 to 63. This can be fixed by swaping the first and second double words. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D94113	2021-01-06 05:56:09 -06:00
Albion Fung	3136cbe29e	[PowerPC] Implement Vector Shift Builtins ... This patch implements the builtins for the vector shifts (shl, srl, sra), and adds the appropriate test cases for these builtins. The builtins utilize the vector shift instructions introduced within ISA 3.1. Differential Revision: https://reviews.llvm.org/D83338	2020-08-12 18:26:58 -05:00