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4 Commits

Author SHA1 Message Date
Qiu Chaofan 2432d80d3b [PowerPC] Use mtvsrdd to put callee-saved GPR into VSR 
This patch exploits mtvsrdd instruction (available in ISA3.0+) to save
two callee-saved GPR registers into a single VSR, making it more
efficient.

Reviewed By: jsji, nemanjai

Differential Revision: https://reviews.llvm.org/D62565
 2021-04-20 16:43:24 +08:00
Fangrui Song 98797a5fc0 [PrologEpilogInserter][test] Improve SpilledToReg test 
D39386 made CalleeSavedInfo possible to spill a register to another register
(vector register for POWER9) but did not actually test live-in.
 2020-10-17 20:36:22 -07:00
Kang Zhang 302e11cd97 [NFC][PowerPC] Fix the liveins for 3 mir test cases 2020-04-24 08:03:02 +00:00
Jinsong Ji 455a0db01a [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 
All tests with -run-pass !=none should not in MIR/, See MIR/README.

```
Tests for codegen passes should NOT be here but in
test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.
```

llvm-svn: 371857
 2019-09-13 14:18:36 +00:00