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Author SHA1 Message Date
Craig Topper 86e604c4d6 [RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates. 
SimplifyDemandedBits can remove set bits from immediates from instructions
like AND/OR/XOR. This can prevent them from being efficiently
codegened on RISCV.

This adds an initial version that tries to keep or form 12 bit
sign extended immediates for AND operations to enable use of ANDI.
If that doesn't work we'll try to create a 32 bit sign extended immediate
to use LUI+ADDIW.

More optimizations are possible for different size immediates or
different operations. But this is a good starting point that already
has test coverage.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D94628
 2021-01-15 11:14:14 -08:00
Michael Munday e28b6a60bc [RISCV][NFC] Regenerate RISCV CodeGen tests 
Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and added @plt to
some symbols.

Differential Revision: https://reviews.llvm.org/D92841
 2020-12-09 19:42:49 +00:00
Luís Marques 5b1d0dc6bf [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
Luís Marques c6b09bff56 [RISCV] Fix wrong CFI directives 
Summary: Removes CFI CFA directives that could incorrectly propagate
beyond the basic block they were inteded for. Specifically it removes
the epilogue CFI directives. See the branch_and_tail_call test for an
example of the issue. Should fix the stack unwinding issues caused by
the incorrect directives.

Reviewers: asb, lenary, shiva0217
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69723
 2019-11-14 18:29:50 +00:00
Luís Marques c5b56caa32 Revert "[RISCV] Fix wrong CFI directives" 
test/DebugInfo/RISCV/relax-debug-frame.ll wasn't properly updated.
 2019-11-13 13:28:33 +00:00
Luís Marques a5ce8bd715 [RISCV] Fix wrong CFI directives 
Summary: Removes CFI CFA directives that could incorrectly propagate
beyond the basic block they were inteded for. Specifically it removes
the epilogue CFI directives. See the branch_and_tail_call test for an
example of the issue. Should fix the stack unwinding issues caused by
the incorrect directives.

Reviewers: asb, lenary, shiva0217
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69723
 2019-11-13 13:06:15 +00:00
Luís Marques be0fead7bf [RISCV][NFC] Add CFI-related tests 
Summary: Adds tests necessary to properly show the impact of other
patches that affect the emission of CFI directives.

Reviewers: asb, lenary
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69721
 2019-11-10 16:00:07 +00:00
Luis Marques 3d0fbafd0b [RISCV] Switch to the Machine Scheduler 
Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revision: https://reviews.llvm.org/D66973

llvm-svn: 372106
 2019-09-17 11:15:35 +00:00
Luis Marques 2d550d19b3 Revert Patch from Phabricator 
This reverts r372092 (git commit e38695a025)

llvm-svn: 372104
 2019-09-17 10:52:09 +00:00
Luis Marques e38695a025 Patch from Phabricator 
llvm-svn: 372092
 2019-09-17 09:43:08 +00:00
Hsiangkai Wang 04ddf39b44 [RISCV] Add CFI directives for RISCV prologue/epilog. 
In order to generate correct debug frame information, it needs to
generate CFI information in prologue and epilog.

Differential Revision: https://reviews.llvm.org/D61773

llvm-svn: 363120
 2019-06-12 03:04:22 +00:00