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Author SHA1 Message Date
Jim Lin 242ddd5089 [RISCV][NFC] Add a single space after comma for VType 
In most of cases, it has a single space after comma in assembly operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103790
 2021-06-09 11:18:22 +08:00
Craig Topper 229eeb187d [RISCV] Look through copies when trying to find an implicit def in addVSetVL. 
The InstrEmitter can sometimes insert a copy after an IMPLICIT_DEF
before connecting it to the vector instruction. This occurs when
constrainRegClass reduces to a class with less than 4 registers.
I believe LMUL8 on masked instructions triggers this since the
result can only use the v8, v16, or v24 register group as the mask
is using v0.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98567
 2021-03-16 07:59:09 -07:00
Craig Topper 45d3ed0304 [RISCV] Add support for scalable vector masked load/store. 
Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98460
 2021-03-12 10:32:33 -08:00