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4 Commits

Author SHA1 Message Date
Craig Topper a33ce06cf5 [RISCV] Improve i32 UADDSAT/USUBSAT on RV64. 
The default promotion uses zero extends that become shifts. We
cam use sign extend instead which is better for RISCV.

I've used two different implementations based on whether we
have minu/maxu instructions.

Differential Revision: https://reviews.llvm.org/D98683
 2021-03-16 07:44:06 -07:00
Craig Topper c91b3c9e63 [RISCV] Fold (select_cc (setlt X, Y), 0, ne, trueV, falseV) -> (select_cc X, Y, lt, trueV, falseV) 
A setcc can be created during LegalizeDAG after select_cc has been
created. This combine will enable us to fold these late setccs.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D98132
 2021-03-07 09:44:56 -08:00
Craig Topper 8860f19034 [RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. 
The expansions of the saturating intrinsics can make use of
the min(u)/max(u) instructions in Zbb.
 2021-02-18 11:41:45 -08:00
Craig Topper acfab44eeb [RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 
There have been some recent changes to the type legalization for
some of these intrinsics so I thought it would be good to have
coverage.
 2021-02-16 11:19:57 -08:00