llvm-project

Commit Graph

Author	SHA1	Message	Date
Kazushi (Jam) Marukawa	44a679eaa4	[VE] Change the behaviour of truncate Change the way to truncate i64 to i32 in I64 registers. VE assumed sext values previously. Change it to zext values this time to make it match to the LLVM behaviour. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92226	2020-11-30 22:12:45 +09:00
Simon Moll	b955c7e630	[VE] VE Vector Predicated SDNode, vector add isel and tests VE Vector Predicated (VVP) SDNodes form an intermediate layer between VE vector instructions and the initial SDNodes. We introduce 'vvp_add' with isel and tests as the first of these VVP nodes. VVP nodes have a mask and explicit vector length operand, which we will make proper use of later. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D91802	2020-11-23 17:17:07 +01:00

Author

SHA1

Message

Date

Kazushi (Jam) Marukawa

44a679eaa4

[VE] Change the behaviour of truncate

Change the way to truncate i64 to i32 in I64 registers.  VE assumed
sext values previously.  Change it to zext values this time to make
it match to the LLVM behaviour.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D92226

2020-11-30 22:12:45 +09:00

Simon Moll

b955c7e630

[VE] VE Vector Predicated SDNode, vector add isel and tests

VE Vector Predicated (VVP) SDNodes form an intermediate layer between VE
vector instructions and the initial SDNodes.

We introduce 'vvp_add' with isel and tests as the first of these VVP
nodes. VVP nodes have a mask and explicit vector length operand, which
we will make proper use of later.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D91802

2020-11-23 17:17:07 +01:00

2 Commits