Craig Topper
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ba6c2a52c7
|
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
llvm-svn: 138034
|
2011-08-19 05:28:50 +00:00 |
|
Eli Friedman
|
0318036c4d
|
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
llvm-svn: 135337
|
2011-07-16 02:41:28 +00:00 |
|
Sean Callanan
|
f2f4837de3
|
Basic sanity checks to ensure that 2- and 3-byte
VEX prefixes are working for triadic AVX
instructions. This concludes the patch set to
enable AVX support for the X86 disassebler.
llvm-svn: 127647
|
2011-03-15 01:32:46 +00:00 |
|
Sean Callanan
|
34770edf43
|
Fixed a bug in the enhanced disassembler that caused
it to ignore valid uses of FS and GS as additional
base registers in address computations. Added a test
case for this.
llvm-svn: 126302
|
2011-02-23 03:31:28 +00:00 |
|
Sean Callanan
|
c1b7775e0f
|
Added a testcase for the enhanced disassembly bug
fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.
llvm-svn: 126182
|
2011-02-22 02:19:18 +00:00 |
|
Rafael Espindola
|
9f9a10691a
|
Correctly disassemble truncated asm.
Patch by Richard Simth.
llvm-svn: 122962
|
2011-01-06 16:48:42 +00:00 |
|
Dale Johannesen
|
2cd8b08207
|
Segregate tests by target.
llvm-svn: 119050
|
2010-11-14 18:14:32 +00:00 |