Commit Graph

6929 Commits

Author SHA1 Message Date
Evan Cheng 5b9b33bcac Reverse branch condition only when there is a conditional branch.
llvm-svn: 71214
2009-05-08 09:35:53 +00:00
Nick Lewycky b873ed672d Add explicit braces to disambiguate nested if/else. Removes a warning.
llvm-svn: 71211
2009-05-08 06:57:41 +00:00
Evan Cheng 2fa281106a Optimize code placement in loop to eliminate unconditional branches or move unconditional branch to the outside of the loop. e.g.
///       A:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       <fallthrough to B>                                                                                                                                                 
///                                                                                                                                                                          
///       B:  --> loop header                                                                                                                                                
///       ...                                                                                                                                                                
///       jcc <cond> C, [exit]                                                                                                                                               
///                                                                                                                                                                          
///       C:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       jmp B                                                                                                                                                              
///                                                                                                                                                                          
/// ==>                                                                                                                                                                      
///                                                                                                                                                                          
///       A:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       jmp B                                                                                                                                                              
///                                                                                                                                                                          
///       C:  --> new loop header                                                                                                                                            
///       ...                                                                                                                                                                
///       <fallthough to B>                                                                                                                                                  
///                                                                                                                                                                          
///       B:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       jcc <cond> C, [exit] 

llvm-svn: 71209
2009-05-08 06:34:09 +00:00
Bob Wilson e20be4183c Fix pr4100. Do not remove no-op copies when they are dead. The register
scavenger gets confused about register liveness if it doesn't see them.
I'm not thrilled with this solution, but it only comes up when there are dead
copies in the code, which is something that hopefully doesn't happen much.

Here is what happens in pr4100: As shown in the following excerpt from the
debug output of llc, the source of a move gets reloaded from the stack,
inserting a new load instruction before the move.  Since that source operand
is a kill, the physical register is free to be reused for the destination
of the move.  The move ends up being a no-op, copying R3 to R3, so it is
deleted.  But, it leaves behind the load to reload %reg1028 into R3, and
that load is not updated to show that it's destination operand (R3) is dead.
The scavenger gets confused by that load because it thinks that R3 is live.

Starting RegAlloc of: %reg1025<def,dead> = MOVr %reg1028<kill>, 14, %reg0, %reg0
  Regs have values: 
  Reloading %reg1028 into R3
  Last use of R3[%reg1028], removing it from live set
  Assigning R3 to %reg1025
  Register R3 [%reg1025] is never used, removing it from live set

Alternative solutions might be either marking the load as dead, or zapping
the load along with the no-op copy.  I couldn't see an easy way to do
either of those, though.

llvm-svn: 71196
2009-05-07 23:47:03 +00:00
Bob Wilson 5352454e6b Fix a comment (again).
llvm-svn: 71180
2009-05-07 21:20:42 +00:00
Bob Wilson 94c0a9fe8e Fix a comment.
llvm-svn: 71179
2009-05-07 21:19:45 +00:00
Dan Gohman 4bb6fa23cb Revert 71165. It did more than just revert 71158 and it introduced
several regressions. The problem due to 71158 is now fixed.

llvm-svn: 71176
2009-05-07 19:46:24 +00:00
Bill Wendling 17f0f65499 Temporarily revert r71158. It was causing a failure during a full bootstrap:
checking for bcopy... no
checking for getc_unlocked... Assertion failed: (0 && "Unknown SCEV kind!"), function operator(), file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~obj/src/lib/Analysis/ScalarEvolution.cpp, line 511.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/libdecnumber/decUtility.c:360: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [decUtility.o] Error 1
make[4]: *** Waiting for unfinished jobs....
Assertion failed: (0 && "Unknown SCEV kind!"), function operator(), file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~obj/src/lib/Analysis/ScalarEvolution.cpp, line 511.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/libdecnumber/decNumber.c:5591: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [decNumber.o] Error 1
make[3]: *** [all-stage2-libdecnumber] Error 2
make[3]: *** Waiting for unfinished jobs....

llvm-svn: 71165
2009-05-07 17:26:14 +00:00
Argyrios Kyrtzidis 58f3811300 Move the tablegen-produced DebugLoc handling into a AsmWriter::processDebugLoc function.
No functionality change.

llvm-svn: 71156
2009-05-07 13:55:51 +00:00
Evan Cheng 143bae5dcd Code refactoring.
llvm-svn: 71151
2009-05-07 05:49:39 +00:00
Evan Cheng f356a89e92 Rename "loop aligner" pass to "code placement optimization" pass.
llvm-svn: 71150
2009-05-07 05:42:24 +00:00
Bill Wendling 5a2fff718d Just turn aggressive stack coloring off at -O3.
llvm-svn: 71140
2009-05-07 01:33:38 +00:00
Bill Wendling 6144f63bd5 Temporarily revert r71010. It was causing massive failures during self-hosting.
llvm-svn: 71138
2009-05-07 01:27:25 +00:00
Argyrios Kyrtzidis baf3fee885 Make DwarfWriter::RecordInlinedFnStart more like the other DwarfWriter's methods:
-Have it return a label ID
-Remove the unused Instruction parameter

No functionality change.

llvm-svn: 71132
2009-05-07 00:16:31 +00:00
Bill Wendling 4d11693f33 - Move some debug fields to coincide with how GCC emits them. No functionality
change.
- Reformatting.

llvm-svn: 71118
2009-05-06 21:21:34 +00:00
Evan Cheng cfc0513080 Do not use register as base ptr of pre- and post- inc/dec load / store nodes.
llvm-svn: 71098
2009-05-06 18:25:01 +00:00
Oscar Fuentes 49518d8f54 CMake: Updated lib/CodeGen/CMakeLists.txt.
llvm-svn: 71085
2009-05-06 14:56:40 +00:00
Duncan Sands 2338f6c57e Add generic expansion of SUB when ADD and XOR
are legal.  Based on a patch by Micah Villmow.

llvm-svn: 71078
2009-05-06 11:29:50 +00:00
Lang Hames ab68cf24bb Renamed Spiller classes (plus uses and related files) to VirtRegRewriter.
llvm-svn: 71057
2009-05-06 02:36:21 +00:00
Dan Gohman bb2f10759e If a MachineBasicBlock has multiple ways of reaching another block,
allow it to have multiple CFG edges to that block. This is needed
to allow MachineBasicBlock::isOnlyReachableByFallthrough to work
correctly. This fixes PR4126.

llvm-svn: 71018
2009-05-05 21:10:19 +00:00
Evan Cheng 9bf9002161 Enable stack coloring with regs at -O3.
llvm-svn: 71010
2009-05-05 20:30:36 +00:00
Chris Lattner 929b644b0f Do not require variable debug info nodes to have a compile unit.
For implicit decls like "self" and "_cmd" in ObjC, these decls
should not have a location.

llvm-svn: 70964
2009-05-05 04:55:56 +00:00
Evan Cheng 6fc03634db Do not substitute if the new register isn't in the register class of the operand being updated.
llvm-svn: 70953
2009-05-05 00:46:16 +00:00
Evan Cheng 1ff2727c95 Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
llvm-svn: 70950
2009-05-05 00:30:09 +00:00
Evan Cheng dbfb102523 Do forward and backward substitution to eliminate loads and stores when possible.
llvm-svn: 70937
2009-05-04 23:13:13 +00:00
Chris Lattner 354b12259f Make DBG_STOPPOINT nodes, and therefore DBG_LABEL labels, get a DebugLoc, so that it
shows up in -print-machineinstrs.  This doesn't appear to affect anything, but it was
weird for some DBG_LABELs to have DebugLocs but not all of them.

llvm-svn: 70921
2009-05-04 22:10:05 +00:00
Argyrios Kyrtzidis 71fb950b73 Restore a comment.
llvm-svn: 70900
2009-05-04 19:23:45 +00:00
Argyrios Kyrtzidis 9ae29b2d8f -Remove the DwarfWriter::RecordSourceLine calls from the instruction selectors.
-Depend on DebugLocs for source line info.

(Comes with Regression-Be-Gone(tm))

llvm-svn: 70871
2009-05-04 16:23:49 +00:00
Evan Cheng 3f77805642 Make sure to color with only allocatable registers for the specific register class.
llvm-svn: 70821
2009-05-04 03:30:11 +00:00
Evan Cheng 4b6072bcb8 The stack slots which share the same stack slot after coloring can, but do not have to, use the same register. In fact, they each may have different register class requirements.
llvm-svn: 70815
2009-05-04 00:24:50 +00:00
Argyrios Kyrtzidis 79be34012f Revert r70803 for now, it causes a regression.
llvm-svn: 70811
2009-05-03 23:27:19 +00:00
Argyrios Kyrtzidis ce7196b903 -Remove the DwarfWriter::RecordSourceLine calls from the instruction selectors.
-Depend on DebugLocs for source line info.

llvm-svn: 70803
2009-05-03 22:03:35 +00:00
Evan Cheng 1de5cf548e Typo.
llvm-svn: 70792
2009-05-03 19:10:11 +00:00
Evan Cheng 210fc62a91 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.

llvm-svn: 70787
2009-05-03 18:32:42 +00:00
Anton Korobeynikov 2745bc92fa Fix typo
llvm-svn: 70770
2009-05-03 13:19:57 +00:00
Anton Korobeynikov 05b7a7c8f8 Properly handle sdiv / udiv / srem / urem libcalls
llvm-svn: 70764
2009-05-03 13:18:16 +00:00
Anton Korobeynikov 399ad444fd Proper name 16 bit libcalls
llvm-svn: 70750
2009-05-03 13:14:08 +00:00
Anton Korobeynikov f3fc92d6fc Add libcall expansion for 16 and 128 bit muls
llvm-svn: 70749
2009-05-03 13:13:51 +00:00
Argyrios Kyrtzidis 97324cec99 -Move the DwarfWriter::ValidDebugInfo check to a static DIDescriptor::ValidDebugInfo
-Create DebugLocs without the need to have a DwarfWriter around

llvm-svn: 70682
2009-05-03 08:50:41 +00:00
Bob Wilson 62a3124fb8 Allow CONCAT_VECTORS nodes to be legal or have custom lowering for some targets.
Changes to take advantage of this will come later.

llvm-svn: 70560
2009-05-01 17:55:32 +00:00
Bill Wendling 80b9abf8f4 Simplify more code and add timer stuff.
llvm-svn: 70539
2009-05-01 08:40:06 +00:00
Bill Wendling 03968bd796 Simplify more code.
llvm-svn: 70537
2009-05-01 08:35:12 +00:00
Bill Wendling 87cbaf4bc9 Simplify some code.
llvm-svn: 70534
2009-05-01 08:32:14 +00:00
Bill Wendling 1c24c74495 Fix whitespace. It was confusing me.
llvm-svn: 70533
2009-05-01 08:25:13 +00:00
Evan Cheng f8949a61bf Code clean up. Bye bye PhysRegTracker.
llvm-svn: 70524
2009-05-01 01:03:49 +00:00
Argyrios Kyrtzidis a5037484a4 Make DebugLoc independent of DwarfWriter.
-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)

llvm-svn: 70520
2009-04-30 23:22:31 +00:00
Jakob Stoklund Olesen 050631c0a6 Join cross class copies using getCommonSubClass()
llvm-svn: 70513
2009-04-30 21:24:03 +00:00
Evan Cheng 007cbe91c5 Add a smarter heuristic to determine when to coalesce a virtual register with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead.
This is *not* turned on by default. Testing indicates this is just as likely to pessimize code. The main issue seems to be allocation preference doesn't work effectively. That will change once I've taught register allocator "swapping".

llvm-svn: 70503
2009-04-30 18:39:57 +00:00
Jay Foad fe0c648fee Move helper functions for optimizing division by constant into the APInt
class.

llvm-svn: 70488
2009-04-30 10:15:35 +00:00
Chris Lattner 5ab42e93c4 fix a regression handling indirect results: these need to be considered
memory operands otherwise the writebacks get lost when the inline asm 
doesn't otherwise have side effects.  This fixes rdar://6839427, though
clang really shouldn't generate these anymore.

llvm-svn: 70455
2009-04-30 00:48:50 +00:00