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5 Commits

Author SHA1 Message Date
Matt Arsenault a6867fd441 AMDGPU: Combine fp16/fp64 subtarget features 
The same control register controls both, and are set to
the same defaults. Keep the old names around as aliases.

llvm-svn: 292837
 2017-01-23 22:31:03 +00:00
Wei Ding 3cb2a1e8d1 AMDGPU : Add a function to enable and disable IEEEBit for SC and shader 
respectively.

Differential Revision: http://reviews.llvm.org/D25789

llvm-svn: 284655
 2016-10-19 22:34:49 +00:00
Sam Kolton a2e5c88baf [AMDGPU] Assembler: rename amd_kernel_code_t asm names according to spec 
Summary:
Also removed duplicate code from AMDGPUTargetAsmStreamer.
This change only change how amd_kernel_code_t is parsed and printed. No variable names are changed.

Reviewers: vpykhtin, tstellarAMD

Subscribers: arsenm, wdng, nhaehnle

Differential Revision: https://reviews.llvm.org/D24296

llvm-svn: 281028
 2016-09-09 10:08:02 +00:00
Matt Arsenault b2cb5f8105 AMDGPU: Simplify tests with per function subtargets 
llvm-svn: 274971
 2016-07-09 07:55:03 +00:00
Matt Arsenault 7293f9895e AMDGPU: Set DX10Clamp bit 
llvm-svn: 259088
 2016-01-28 20:53:35 +00:00