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Author SHA1 Message Date
Alex Bradbury ee7c7ecd03 [RISCV] Prepare for the use of variable-sized register classes 
While parameterising by XLen, also take the opportunity to clean up the 
formatting of the RISCV .td files.

This commit unifies the in-tree code with my patchset at 
<https://github.com/lowrisc/riscv-llvm>.

llvm-svn: 316159
 2017-10-19 14:29:03 +00:00
Alex Bradbury 8ab4a9696a [RISCV] Add support for disassembly 
This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s
has been updated appropriately.

Differential Revision: https://reviews.llvm.org/D23567

llvm-svn: 313486
 2017-09-17 14:36:28 +00:00