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3 Commits

Author SHA1 Message Date
Alex Bradbury 8c345c5aa9 [RISCV] MC layer support for the standard RV32A instruction set extension 
llvm-svn: 317791
 2017-11-09 15:00:03 +00:00
Alex Bradbury a47514ce3f [RISCV] MC layer support for the standard RV32M instruction set extension 
llvm-svn: 317788
 2017-11-09 14:46:30 +00:00
Alex Bradbury 8971842f43 [RISCV] Initial codegen support for ALU operations 
This adds the minimum necessary to support codegen for simple ALU operations
on RV32. Prolog and epilog insertion, support for memory operations etc etc 
follow in future patches.

Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is 
reviewed and lands.

Differential Revision: https://reviews.llvm.org/D29933

llvm-svn: 316188
 2017-10-19 21:37:38 +00:00