bfebd1fc7e
R600: Enable vector fpow.
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The OpenCL specs say: "The vector versions of the math functions operate
component-wise. The description is per-component."
Patch by: Jan Vesely
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 200773
2014-02-04 17:18:37 +00:00
f143af3fe9
R600: Use function inputs to represent data stored in gpr
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llvm-svn: 194425
2013-11-11 22:10:24 +00:00
77a8352476
R600: Support schedule and packetization of trans-only inst
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llvm-svn: 185268
2013-06-29 19:32:43 +00:00
4b5b849753
R600: Schedule copy from phys register at beginning of block
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It allows regalloc pass to remove them by trivially assigning associated reg
llvm-svn: 183336
2013-06-05 20:27:35 +00:00
f83df1f1cb
R600: use capital letter for PV channel
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llvm-svn: 183107
2013-06-03 15:44:35 +00:00
3d5118ca40
R600: Use bottom up scheduling algorithm
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llvm-svn: 182129
2013-05-17 16:50:56 +00:00
f97af796a9
R600: Prettier asmPrint of Alu
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llvm-svn: 180956
2013-05-02 21:52:30 +00:00
3de8ae38e6
R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730
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llvm-svn: 177736
2013-03-22 15:24:16 +00:00
75aadc2813
Add R600 backend
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A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
llvm-svn: 169915
2012-12-11 21:25:42 +00:00
Tom Stellard