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265 Commits

Author SHA1 Message Date
Owen Anderson 2aedba6c5e Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. 
llvm-svn: 136141
 2011-07-26 20:54:26 +00:00
Evan Cheng 61faa55b74 Separate MCInstPrinter registration from AsmPrinter registration. 
llvm-svn: 135974
 2011-07-25 21:20:24 +00:00
Evan Cheng a20cde31e7 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. 
llvm-svn: 135636
 2011-07-20 23:34:39 +00:00
Jim Grosbach 204c128f66 Use tPseudoExpand for tTAILJMPrND and tTAILJMPr. 
llvm-svn: 134734
 2011-07-08 20:39:19 +00:00
Jim Grosbach 4af8647e17 Use tPseudoExpand for tTAILJMPd and tTAILJMPdND. 
llvm-svn: 134732
 2011-07-08 20:32:21 +00:00
Jim Grosbach dbfb29d6c0 Use ARMPseudoExpand for ARM tail calls. 
llvm-svn: 134719
 2011-07-08 18:50:22 +00:00
Jim Grosbach 2dfe8e3ccd Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred. 
TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712
 2011-07-08 18:15:12 +00:00
Jim Grosbach 95dee40343 Use TableGen'erated pseudo lowering for ARM. 
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.

llvm-svn: 134705
 2011-07-08 17:40:42 +00:00
Cameron Zwarich 148220306f The VMLA instruction and its friends are not actually fused; they're plain old 
multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609
 2011-07-07 08:28:52 +00:00
Evan Cheng ab37af9af3 createMCInstPrinter doesn't need TargetMachine anymore. 
llvm-svn: 134525
 2011-07-06 19:45:42 +00:00
Jim Grosbach e9cc901814 Refact ARM Thumb1 tMOVr instruction family. 
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.

llvm-svn: 134204
 2011-06-30 23:38:17 +00:00
Jim Grosbach b98ab91e39 Thumb1 register to register MOV instruction is predicable. 
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.

llvm-svn: 134197
 2011-06-30 22:10:46 +00:00
Jim Grosbach 353da73186 Pseudo-ize the t2LDMIA_RET instruction. 
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.

llvm-svn: 134173
 2011-06-30 18:25:42 +00:00
Jim Grosbach 417671a7b1 Pseudo-ize the Thumb tPOP_RET instruction. 
It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.

llvm-svn: 134172
 2011-06-30 17:34:04 +00:00
Jim Grosbach a8a8067dec Remove redundant Thumb2 ADD/SUB SP instruction definitions. 
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.

llvm-svn: 134114
 2011-06-29 23:25:04 +00:00
Eric Christopher d00e8ad803 Implement the 'M' output modifier for arm inline asm. This is fairly 
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.

rdar://9119939

llvm-svn: 132242
 2011-05-28 01:40:44 +00:00
Rafael Espindola d23bfb8a7a Make size computation less brittle. 
llvm-svn: 132222
 2011-05-27 22:05:41 +00:00
Eric Christopher 33a73c7755 Reorganize these slightly according to operand type. 
llvm-svn: 132128
 2011-05-26 18:22:26 +00:00
Cameron Zwarich 26ddb12118 Mark tBX as an indirect branch rather than a return. 
llvm-svn: 132107
 2011-05-26 03:41:12 +00:00
Cameron Zwarich a946f476d3 Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions. 
llvm-svn: 132086
 2011-05-25 21:53:50 +00:00
Eric Christopher 8c5e4192e6 Implement the 'm' modifier. Note that it only works for memory operands. 
Part of rdar://9119939

llvm-svn: 132081
 2011-05-25 20:51:58 +00:00
Cameron Zwarich 3088e0a179 Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This 
fixes <rdar://problem/9495913>

llvm-svn: 132042
 2011-05-25 04:45:27 +00:00
Cameron Zwarich deaf994ff0 Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better 
reflect their actual meaning and match the ARM instructions.

llvm-svn: 132039
 2011-05-25 04:45:14 +00:00
Eric Christopher 1b724948e9 Implement the arm 'L' asm modifier. 
Part of rdar://9119939

llvm-svn: 132024
 2011-05-24 23:27:13 +00:00
Eric Christopher b1dda56ac2 Implement the immediate part of the 'B' modifier. 
Part of rdar://9119939

llvm-svn: 132023
 2011-05-24 23:15:43 +00:00
Eric Christopher d4562566b4 Add more unimplemented asm modifiers and some documentation of what they 
do.

Part of rdar://9119939.

llvm-svn: 132015
 2011-05-24 22:27:43 +00:00
Eric Christopher 7617883ce3 Add support for the arm 'y' asm modifier. 
Fixes part of rdar://9444657

llvm-svn: 132011
 2011-05-24 22:10:34 +00:00
Cameron Zwarich bc90690b24 Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches 
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.

llvm-svn: 131894
 2011-05-23 01:57:17 +00:00
Rafael Espindola 652bfdb1ab adds some attributes to attribute section when cpu is "xscale" 
(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

llvm-svn: 131751
 2011-05-20 20:10:34 +00:00
Rafael Espindola e90c1cb221 sets bit 0 of the function address of thumb function in .symtab 
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)

Patch by Koan-Sin Tan!

llvm-svn: 131406
 2011-05-16 16:17:21 +00:00
Devang Patel 39ecf816c5 Do not emit location expression size twice. 
llvm-svn: 130854
 2011-05-04 19:00:57 +00:00
Devang Patel 3e021533cd Teach dwarf writer to handle complex address expression for .debug_loc entries. 
This fixes clang generated blocks' variables' debug info.
Radar 9279956.

llvm-svn: 130373
 2011-04-28 02:22:40 +00:00
Devang Patel e3745fdcf3 Revert r130178. It turned out to be not the optimal path to emit complex location expressions. 
llvm-svn: 130326
 2011-04-27 20:29:27 +00:00
Devang Patel cae2fbd6fc Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables. 
llvm-svn: 130178
 2011-04-26 00:12:46 +00:00
Devang Patel 3c39ec2933 Add asserts. 
llvm-svn: 129995
 2011-04-22 16:44:29 +00:00
Devang Patel 94ad6ac13c Fix DWARF description of Q registers. 
llvm-svn: 129952
 2011-04-21 23:22:35 +00:00
Devang Patel 3712c14be9 Fix DWARF description of S registers. 
llvm-svn: 129947
 2011-04-21 22:48:26 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Bill Wendling 00f0cddfd4 We need to pass the TargetMachine object to the InstPrinter if we are printing 
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.

This is part of a work-in-progress.

llvm-svn: 127986
 2011-03-21 04:13:46 +00:00
Jim Grosbach 3af6fe66b9 Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches. 
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).

llvm-svn: 127637
 2011-03-15 00:30:40 +00:00
Jim Grosbach 3f2096eafe Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same 
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.

llvm-svn: 127515
 2011-03-12 00:45:26 +00:00
Jim Grosbach f026d9ed53 Pseudo-ize the ARM 'B' instruction. 
llvm-svn: 127510
 2011-03-11 23:24:15 +00:00
Jim Grosbach 6d371ce37e Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side- 
effect that we get proper instruction printing using the "pop" mnemonic for it.

llvm-svn: 127502
 2011-03-11 22:51:41 +00:00
Anton Korobeynikov 692f633df9 ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case 
llvm-svn: 127106
 2011-03-05 18:44:00 +00:00
Anton Korobeynikov 9e66cbb366 In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue. 
llvm-svn: 127105
 2011-03-05 18:43:55 +00:00
Anton Korobeynikov a8d177b2d4 Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. 
llvm-svn: 127104
 2011-03-05 18:43:50 +00:00
Anton Korobeynikov 51537f1c7f Add unwind information emission for thumb stuff 
llvm-svn: 127103
 2011-03-05 18:43:43 +00:00
Anton Korobeynikov e7410dd0d5 Preliminary support for ARM frame save directives emission via MI flags. 
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.

llvm-svn: 127101
 2011-03-05 18:43:32 +00:00
Renato Golin e84af17b6e Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard. 
llvm-svn: 126882
 2011-03-02 21:20:09 +00:00
Renato Golin ec0fc7d842 Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931 
llvm-svn: 126689
 2011-02-28 22:04:27 +00:00