db429d9483
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
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These exception-related opcodes are not used any longer.
llvm-svn: 185625
2013-07-04 13:54:20 +00:00
a1f5b901a5
Revert r185595-185596 which broke buildbots.
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Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
llvm-svn: 185600
2013-07-04 00:26:30 +00:00
f33ec531fa
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
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These exception-related opcodes are not used any longer.
llvm-svn: 185596
2013-07-03 23:56:31 +00:00
1af66c9b8a
[mips] Reverse the order of source operands of shift and rotate instructions that
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have three register operands.
No intended functionality changes.
llvm-svn: 185376
2013-07-01 20:39:53 +00:00
295bd43adb
The getRegForInlineAsmConstraint function should only accept MVT value types.
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llvm-svn: 184642
2013-06-22 18:37:38 +00:00
2bf97336af
[mips] Big-endian code generation for atomic instructions.
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Patch by Jyun-Yan You.
llvm-svn: 182984
2013-05-31 03:25:44 +00:00
ad6d08ac6f
Order CALLSEQ_START and CALLSEQ_END nodes.
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Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
llvm-svn: 182885
2013-05-29 22:03:55 +00:00
ef9de2a739
Track IR ordering of SelectionDAG nodes 2/4.
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Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
llvm-svn: 182703
2013-05-25 02:42:55 +00:00
df1ecbd734
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
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llvm-svn: 182680
2013-05-24 22:23:49 +00:00
be76cd0b8e
[mips] Rename option to make it compatible with gcc.
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llvm-svn: 182397
2013-05-21 17:17:59 +00:00
1cb024207f
[mips] Trap on integer division by zero.
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By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.
llvm-svn: 182306
2013-05-20 18:07:43 +00:00
75865923c9
Add LLVMContext argument to getSetCCResultType
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llvm-svn: 182180
2013-05-18 00:21:46 +00:00
252f54f769
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).
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Previously, three instructions were needed:
trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)
Now we need only two:
trunc.w.s $f0, $f2
swc1 $f0, 0($2)
llvm-svn: 182053
2013-05-16 21:17:15 +00:00
d82ee940c3
[mips] Factor out unaligned store lowering code.
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llvm-svn: 182050
2013-05-16 20:45:17 +00:00
7b6e4f1366
[mips] Delete unused enum value.
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llvm-svn: 182035
2013-05-16 18:40:12 +00:00
783c79446b
Checkin in of first of several patches to finish implementation of
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mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
llvm-svn: 181641
2013-05-10 22:25:39 +00:00
4254319ef9
[mips] Fix handling of instructions which copy to/from accumulator registers.
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Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.
llvm-svn: 180827
2013-04-30 23:22:09 +00:00
68741cc38d
[mips] Instruction selection patterns for DSP-ASE vector select and compare
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instructions.
llvm-svn: 180820
2013-04-30 22:37:26 +00:00
9da442f506
[mips] Simplify code.
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No intended functionality changes.
llvm-svn: 180807
2013-04-30 21:17:07 +00:00
a2b533906a
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
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llvm-svn: 179939
2013-04-20 12:32:17 +00:00
1ebb2a1c56
[mips] Instruction selection patterns for DSP-ASE vector shifts.
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llvm-svn: 179906
2013-04-19 23:21:32 +00:00
89af58991a
[mips] Rename function.
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llvm-svn: 179741
2013-04-18 01:00:46 +00:00
a6bbde5839
[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and
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lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering.
No functionality changes.
llvm-svn: 179444
2013-04-13 02:13:30 +00:00
52f79fcdae
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.
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- Rename function.
- Pass iterator by value.
- Remove header include.
No functionality changes.
llvm-svn: 179312
2013-04-11 19:07:14 +00:00
fb221c197d
[mips] Fix DSP instructions to have explicit accumulator register operands.
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Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.
llvm-svn: 178406
2013-03-30 01:58:00 +00:00
9efcd76c2c
[mips] Move the code which does dag-combine for multiply-add/sub nodes to
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derived class MipsSETargetLowering.
We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.
llvm-svn: 178404
2013-03-30 01:42:24 +00:00
be8612f6f4
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
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The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.
Mips16's instructions are unaffected by this change.
llvm-svn: 178403
2013-03-30 01:36:35 +00:00
f0ea500c14
[mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.
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llvm-svn: 178396
2013-03-30 01:16:38 +00:00
d5a0e096bc
Fix indentation.
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llvm-svn: 178395
2013-03-30 01:15:17 +00:00
28721bd7dd
[mips] Add mips-specific nodes which will be used to select multiply and divide
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instructions.
llvm-svn: 178394
2013-03-30 01:14:04 +00:00
96ca182904
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for
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mips16 and MipsSETargetLowering is for mips32/64.
No functionality changes.
llvm-svn: 176917
2013-03-13 00:54:29 +00:00
0bb60d8972
[mips] Rename function and variable names to start with proper case. Fix typos.
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Delete commented-out code.
llvm-svn: 176844
2013-03-12 00:16:36 +00:00
b1588fc057
DAGCombiner: Use correct value type for checking legality of BR_CC v3
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LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.
v2:
- Expand more BR_CC value types for NVPTX
v3:
- Expand correct BR_CC value types for Hexagon, Mips, and XCore.
llvm-svn: 176694
2013-03-08 15:36:57 +00:00
0f693a8a77
[mips] Custom-legalize BR_JT.
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In N64-static, GOT address is needed to compute the branch address.
llvm-svn: 176580
2013-03-06 21:32:03 +00:00
e092f72956
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets
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returned in registers $2 and $4.
llvm-svn: 176527
2013-03-05 22:54:59 +00:00
5f3ba9e595
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly
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handle fp128 returns.
llvm-svn: 176523
2013-03-05 22:41:55 +00:00
3b7391d140
[mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floating
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point registers.
llvm-svn: 176521
2013-03-05 22:20:28 +00:00
4b634fa3b3
[mips] Correct handling of fp128 (long double) formals and read long double
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parameters from floating point registers if target is mips64 hard float.
llvm-svn: 176520
2013-03-05 22:13:04 +00:00
0e149b04f6
Mips specific inline assembler constraint 'R'
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'R' An address that can be sued in a non-macro load or store.
This patch includes a positive test case.
llvm-svn: 176452
2013-03-04 21:33:15 +00:00
434874db6f
Mips ISD typo
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llvm-svn: 176426
2013-03-04 01:06:54 +00:00
bd1058a877
Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.
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llvm-svn: 176007
2013-02-25 02:25:47 +00:00
7a86b3dc2b
Make psuedo FEXT_T8I816_ins into a custom emitter.
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llvm-svn: 176002
2013-02-24 23:17:51 +00:00
e2bead7a2d
Make psuedo FEXT_T8I816_ins a custom inserter. It should be expanded
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as early as possible; which means during instruction selection.
llvm-svn: 175984
2013-02-24 06:16:39 +00:00
dacee2bb44
Expand pseudos/macros for Selt. This is the last of the complex
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macros.The rest is some small misc. stuff.
llvm-svn: 175950
2013-02-23 03:09:56 +00:00
02b0e48f6a
[mips] Emit call16 operator instead of got_disp. The former allows lazy binding.
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llvm-svn: 175920
2013-02-22 21:10:03 +00:00
fbe4e863db
Fix a nomenclature mistake. Slt->Slti in the functions. The "i" refers
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to the immediate operand of sli or cmp function.
llvm-svn: 175865
2013-02-22 05:59:39 +00:00
4416cdadd5
Expand mips16 SelT form pseudso/macros.
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llvm-svn: 175862
2013-02-22 05:10:51 +00:00
97ba5f2772
Expand the sel pseudo/macro. This generates basic blocks where previously
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there were inline br .+4 instructions. Soon everything can enjoy the
full instruction scheduling experience.
llvm-svn: 175718
2013-02-21 04:22:38 +00:00
341ad3e72a
Update TargetLowering ivars for name policy.
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http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.
No functional change intended.
llvm-svn: 175667
2013-02-20 21:13:59 +00:00
5001be54ad
[mips] Clean up class MipsCCInfo.
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No functionality change intended.
llvm-svn: 175310
2013-02-15 21:45:11 +00:00
Jakob Stoklund Olesen