0099744506
pull byval processing out to its own helper function.
...
llvm-svn: 122235
2010-12-20 07:57:41 +00:00
7394680a00
fix PR8769, a miscompilation by inliner when inlining a function with a byval
...
argument. The generated alloca has to have at least the alignment of the
byval, if not, the client may be making assumptions that the new alloca won't
satisfy.
llvm-svn: 122234
2010-12-20 07:45:28 +00:00
4ffda706d0
MachineVerifier should count landing pad successors as basic blocks rather than
...
out-edges. Fixes PR8824.
llvm-svn: 122228
2010-12-20 04:19:48 +00:00
660bce67f3
Teach MachineVerifier that early clobber defs begin at USE slots and other defs
...
begin at DEF slots. Fixes the second half of PR8813.
llvm-svn: 122225
2010-12-20 03:15:20 +00:00
bc2461c5f9
Add a missing check from r122218.
...
llvm-svn: 122224
2010-12-20 02:59:51 +00:00
0b3ca50ebb
implement type legalization promotion support for SMULO and UMULO, giving
...
ARM (and other 32-bit-only) targets support for i8 and i16 overflow
multiplies. The generated code isn't great, but this at least fixes
CodeGen/Generic/overflow.ll when running on ARM hosts.
llvm-svn: 122221
2010-12-20 02:05:39 +00:00
5c00d41688
now that addc/adde are gone, "ADDC" in the X86 backend uses EFLAGS results,
...
the same as setcc. Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS). This is
a step towards finishing off PR5443. In the testcase in that bug we now get:
movq %rdi, %rax
addq %rsi, %rax
sbbq %rcx, %rcx
testb $1, %cl
setne %dl
ret
instead of:
movq %rdi, %rax
addq %rsi, %rax
movl $0, %ecx
adcq $0, %rcx
testq %rcx, %rcx
setne %dl
ret
llvm-svn: 122219
2010-12-20 01:37:09 +00:00
fc0c6b1ea9
Don't assume that an instruction ending a register's live range always reads
...
the register; it may be a dead def instead. Fixes PR8820.
llvm-svn: 122218
2010-12-20 01:22:37 +00:00
46b9efcad7
We lower setb to sbb with the hope that the and will go away, when it
...
doesn't, match it back to setb.
On a 64-bit version of the testcase before we'd get:
movq %rdi, %rax
addq %rsi, %rax
sbbb %dl, %dl
andb $1, %dl
ret
now we get:
movq %rdi, %rax
addq %rsi, %rax
setb %dl
ret
llvm-svn: 122217
2010-12-20 01:16:03 +00:00
1991c47ec1
Avoid dropping the address space when InstCombine optimizes memset
...
llvm-svn: 122215
2010-12-20 01:05:30 +00:00
9c26d2711b
use for loop over types.
...
llvm-svn: 122214
2010-12-20 01:03:27 +00:00
846c20d4e6
Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which
...
their carry depenedencies with MVT::Flag operands) and use clean and beautiful
EFLAGS dependences instead.
We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs
(which is what requires the previous scheduler change) and change X86 ISelLowering
to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes.
With the previous series of changes, this causes no changes in the testsuite, woo.
llvm-svn: 122213
2010-12-20 00:59:46 +00:00
981afd206b
Fix a bug in the scheduler's handling of "unspillable" vregs.
...
Imagine we see:
EFLAGS = inst1
EFLAGS = inst2 FLAGS
gpr = inst3 EFLAGS
Previously, we would refuse to schedule inst2 because it clobbers
the EFLAGS of the predecessor. However, it also uses the EFLAGS
of the predecessor, so it is safe to emit. SDep edges ensure that
the right order happens already anyway.
This fixes 2 testsuite crashes with the X86 patch I'm going to
commit next.
llvm-svn: 122211
2010-12-20 00:55:43 +00:00
0cfe884874
the result of CheckForLiveRegDef is dead, remove it.
...
llvm-svn: 122209
2010-12-20 00:51:56 +00:00
ed69c6e4b9
reduce indentation, no functionality change.
...
llvm-svn: 122208
2010-12-20 00:50:16 +00:00
1b67d6c565
Ignore debug values when performing MachineVerifier liveness checks. Fixes
...
PR8822.
llvm-svn: 122207
2010-12-20 00:08:10 +00:00
1064992c84
Prevents PerformShuffleCombine from creating a node with an illegal type after legalize types
...
has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type.
llvm-svn: 122206
2010-12-19 23:55:53 +00:00
0b111b1aee
Early clobber operands are allowed to be defined at use indices. This fixes one
...
half of PR8813.
llvm-svn: 122205
2010-12-19 23:50:53 +00:00
4fb9dd4c74
fix an oversight caught by Frits!
...
llvm-svn: 122204
2010-12-19 23:24:04 +00:00
251337e1c4
Fix PR8815 by checking for an explicit clobber def tied to a use operand in
...
ConnectedVNInfoEqClasses::Classify().
llvm-svn: 122202
2010-12-19 22:12:45 +00:00
9edf3f50bf
improve the setcc -> setcc_carry optimization to happen more
...
consistently by moving it out of lowering into dag combine.
Add some missing patterns for matching away extended versions of setcc_c.
llvm-svn: 122201
2010-12-19 22:08:31 +00:00
7e24173a3c
Fix PR8811 by teaching MachineVerifier about optional defs.
...
llvm-svn: 122199
2010-12-19 21:37:23 +00:00
b5cec4f11a
StrongPHIElimination will never run before TwoAddressInstructionPass.
...
llvm-svn: 122197
2010-12-19 21:32:29 +00:00
6dddab2ffe
simplify some code to just reuse a setcc if we can instead of
...
going through the CSE maps to get it.
llvm-svn: 122196
2010-12-19 21:23:48 +00:00
0de20af7ba
Add missing standard headers. Patch by Joerg Sonnenberger!
...
llvm-svn: 122193
2010-12-19 20:43:38 +00:00
b71afe82bf
Add missing std:: prefixes to some calls. C++ doesn't require that <cfoo>
...
headers provide symbols outside namespace std and the LLVM coding standards
state that we should prefix all of them.
llvm-svn: 122192
2010-12-19 20:42:43 +00:00
440b2804ff
teach MaskedValueIsZero how to analyze ADDE. This is
...
enough to teach it that ADDE(0,0) is known 0 except the
low bit, for example.
llvm-svn: 122191
2010-12-19 20:38:28 +00:00
b6252a376a
tidy up
...
llvm-svn: 122190
2010-12-19 20:24:28 +00:00
c37bb023b1
now that generic vector types aren't selected onto MMX operations,
...
we don't need -disable-mmx anymore.
llvm-svn: 122189
2010-12-19 20:19:20 +00:00
ae756e1980
reduce copy/paste programming with the power of for loops.
...
llvm-svn: 122187
2010-12-19 20:07:10 +00:00
1e8c032a6e
X86 supports i8/i16 overflow ops (except i8 multiplies), we should
...
generate them.
Now we compile:
define zeroext i8 @X(i8 signext %a, i8 signext %b) nounwind ssp {
entry:
%0 = tail call %0 @llvm.sadd.with.overflow.i8(i8 %a, i8 %b)
%cmp = extractvalue %0 %0, 1
br i1 %cmp, label %if.then, label %if.end
into:
_X: ## @X
## BB#0: ## %entry
subl $12, %esp
movb 16(%esp), %al
addb 20(%esp), %al
jo LBB0_2
Before we were generating:
_X: ## @X
## BB#0: ## %entry
pushl %ebp
movl %esp, %ebp
subl $8, %esp
movb 12(%ebp), %al
testb %al, %al
setge %cl
movb 8(%ebp), %dl
testb %dl, %dl
setge %ah
cmpb %cl, %ah
sete %cl
addb %al, %dl
testb %dl, %dl
setge %al
cmpb %al, %ah
setne %al
andb %cl, %al
testb %al, %al
jne LBB0_2
llvm-svn: 122186
2010-12-19 20:03:11 +00:00
3e635d2e99
move a transformation to a more logical place, simplifying it.
...
llvm-svn: 122183
2010-12-19 19:43:52 +00:00
5e0c0c72e9
recognize an unsigned add with overflow idiom into uadd.
...
This resolves a README entry and technically resolves PR4916,
but we still get poor code for the testcase in that PR because
GVN isn't CSE'ing uadd with add, filed as PR8817.
Previously we got:
_test7: ## @test7
addq %rsi, %rdi
cmpq %rdi, %rsi
movl $42, %eax
cmovaq %rsi, %rax
ret
Now we get:
_test7: ## @test7
addq %rsi, %rdi
movl $42, %eax
cmovbq %rsi, %rax
ret
llvm-svn: 122182
2010-12-19 19:37:52 +00:00
33dc3f0cfa
optimize uadd(x, cst) into a comparison when the normal
...
result is dead. This is required for my next patch to not
regress the testsuite.
llvm-svn: 122181
2010-12-19 19:35:32 +00:00
ce2995ae58
use IC.ReplaceInstUsesWith instead of a raw RAUW so that uses of
...
the old thing end up on the instcombine worklist. Not doing this
can cause an extra top-level iteration of instcombine, burning
compile time.
llvm-svn: 122179
2010-12-19 18:38:44 +00:00
79874566ce
generalize the sadd creation code to not require that the
...
sadd formed is half the size of the original type. We can
now compile this into a sadd.i8:
unsigned char X(char a, char b) {
int res = a+b;
if ((unsigned )(res+128) > 255U)
abort();
return res;
}
llvm-svn: 122178
2010-12-19 18:35:09 +00:00
c56c845377
fix another miscompile in the llvm.sadd formation logic: it wasn't
...
checking to see if the high bits of the original add result were dead.
Inserting a smaller add and zexting back to that size is not good enough.
This is likely to be the fix for 8816.
llvm-svn: 122177
2010-12-19 18:22:06 +00:00
713ab37965
Remove some checks for StrongPHIElim. These checks make it impossible to use an
...
alternative register allocator that does not require LiveIntervals by specifying
it on the command-line for a target that has StrongPHIElimination enabled by
default.
These checks are pretty meaningless anyways, since StrongPHIElimination and
PHIElimination are never used at the same time.
llvm-svn: 122176
2010-12-19 18:03:27 +00:00
f29562db25
fix a bug (possibly 8816) in the sadd forming xform: it isn't
...
profitable (or safe) to promote code when the add-with-constant
has other uses.
llvm-svn: 122175
2010-12-19 17:59:02 +00:00
ee61c1d820
rework the code added in r122072 to pull it out to its own
...
helper function, clean up comments, and reduce indentation.
No functionality change.
llvm-svn: 122174
2010-12-19 17:52:50 +00:00
408a684d29
Enhance LICM to promote alias sets whose pointers themselves are stored,
...
which doesn't affect the memory address being promoted.
llvm-svn: 122172
2010-12-19 05:57:25 +00:00
3337a81450
fix PR8602, a bug in an assertion: a volatile store *of* a pointer
...
does not make the alias set for that pointer volatile, just stores
*to* the pointer.
llvm-svn: 122171
2010-12-19 05:51:54 +00:00
77a8a71414
fix PR8642: if a critical edge has a PHI value that can trap,
...
isel is *required* to split the edge. PHI values get evaluated
on the edge, not in their predecessor block.
llvm-svn: 122170
2010-12-19 04:58:57 +00:00
fb888622c3
revert r122164, I'm going to go with a different approach.
...
llvm-svn: 122168
2010-12-19 04:23:03 +00:00
ee54636f0a
Fixed version of 122160 (the previous one would fold undefined symbols).
...
llvm-svn: 122167
2010-12-19 04:18:56 +00:00
9a2d4e04c7
Revert 122160 while I debug it.
...
llvm-svn: 122165
2010-12-19 03:22:05 +00:00
583ec6fa44
first step to fixing PR8642: don't fold away empty basic blocks
...
which have trapping constant exprs in them due to PHI nodes.
Eliminating them can cause the constant expr to be evalutated
on new paths if the input edges are critical.
llvm-svn: 122164
2010-12-19 03:02:34 +00:00
6fd80a5593
Move all folding to AttemptToFoldSymbolOffsetDifference.
...
llvm-svn: 122160
2010-12-19 02:15:04 +00:00
fce1fe16e0
Fix whitespace.
...
llvm-svn: 122158
2010-12-18 22:23:15 +00:00
ca93d8406d
Support/PathV1: Deprecate get{Basename,Dirname,Suffix}.
...
llvm-svn: 122157
2010-12-18 22:23:07 +00:00
6b8b4855ff
simplify this a bit.
...
llvm-svn: 122156
2010-12-18 20:22:49 +00:00
3eb4fedecf
Restore the behavior of frame lowering before my refactoring.
...
It turns out that ppc backend has really weird interdependencies
over different hooks and all stuff is fragile wrt small changes.
This should fix PR8749
llvm-svn: 122155
2010-12-18 19:53:14 +00:00
71d29167ea
Add support for lexing single quotes like 'c'.
...
This fixed 8615.
llvm-svn: 122150
2010-12-18 08:56:37 +00:00
c15ab07cff
Revert r122143 through r122140, which collectively broke the LLVMC tests on
...
the buildbots.
llvm-svn: 122149
2010-12-18 07:37:18 +00:00
b403e098a1
Merge isAbsolute into IsSymbolRefDifferenceFullyResolved.
...
llvm-svn: 122148
2010-12-18 06:27:54 +00:00
8396dd0893
Remove the MCObjectFormat class.
...
llvm-svn: 122147
2010-12-18 05:37:28 +00:00
293a7c1840
Add a FIXME and explain a hack.
...
llvm-svn: 122144
2010-12-18 04:19:20 +00:00
01cf728ea9
Fix whitespace.
...
llvm-svn: 122142
2010-12-18 04:13:46 +00:00
4f63507d05
Support/PathV1: Deprecate get{Basename,Dirname,Suffix}.
...
llvm-svn: 122141
2010-12-18 04:13:36 +00:00
1ea7f18caa
Fix the note.
...
llvm-svn: 122139
2010-12-18 04:01:45 +00:00
5004f4a9b5
Revert 122011, 122012, 122013, 122023 adding back an important optimization.
...
I added a note, but suggestions on how to add a test are really welcome.
llvm-svn: 122138
2010-12-18 03:57:21 +00:00
1fa7958eaa
Apparently, operandices is not a word.
...
llvm-svn: 122135
2010-12-18 03:28:32 +00:00
fdaae0d16f
Move some data to the TargetWriter.
...
llvm-svn: 122134
2010-12-18 03:27:34 +00:00
3b2966dc7d
Teach the inline spiller to attempt folding a load instruction into its single
...
use before rematerializing the load.
This allows us to produce:
addps LCPI0_1(%rip), %xmm2
Instead of:
movaps LCPI0_1(%rip), %xmm3
addps %xmm3, %xmm2
Saving a register and an instruction. The standard spiller already knows how to
do this.
llvm-svn: 122133
2010-12-18 03:04:14 +00:00
2a9f194b00
Tweak debug spew.
...
llvm-svn: 122132
2010-12-18 03:04:11 +00:00
429bb1e2cc
r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to
...
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.
There is a test case, but unfortunately it's sensitive to random code changes.
<rdar://problem/8782223>
llvm-svn: 122131
2010-12-18 02:13:59 +00:00
a4dda53686
RemoveUnusedCPEntries can change things. Track it.
...
llvm-svn: 122129
2010-12-18 01:53:06 +00:00
7971a3eaff
Check that the register is live-in to the loop header before inserting copies in
...
the loop predecessors.
The register can be live-out from a predecessor without being live-in to the
loop header if there is a critical edge from the predecessor.
llvm-svn: 122123
2010-12-18 01:06:19 +00:00
1d108cb962
Fix GCC warning:
...
lib/CodeGen/RegAllocGreedy.cpp:311: error: unused variable 'PhysReg' [-Wunused-variable]
llvm-svn: 122122
2010-12-18 01:05:55 +00:00
625ccf8222
Relax push instructions.
...
llvm-svn: 122121
2010-12-18 01:01:34 +00:00
55a700b0cf
Make LazyValueInfo non-recursive.
...
llvm-svn: 122120
2010-12-18 01:00:40 +00:00
eda2a9ec89
Rearrange some Neon multiclasses. No functional changes.
...
llvm-svn: 122119
2010-12-18 00:42:58 +00:00
762a55b19f
Support/PathV1: Deprecate getLast.
...
llvm-svn: 122116
2010-12-18 00:19:10 +00:00
e663aeacf9
Add support to CallbackVH to receive notification when a Value's use-list changes.
...
llvm-svn: 122114
2010-12-18 00:07:15 +00:00
bf4550e3fb
Pass a Banner argument to the machine code verifier both from
...
createMachineVerifierPass and MachineFunction::verify.
The banner is printed before the machine code dump, just like the printer pass.
llvm-svn: 122113
2010-12-18 00:06:56 +00:00
00871c71e9
Fix result type of Neon floating-point comparisons against zero.
...
The result vector elements are always integers. Radar 8782191.
llvm-svn: 122112
2010-12-18 00:04:33 +00:00
f268d0303b
Add some missing entries in ARMTargetLowering::getTargetNodeName.
...
llvm-svn: 122111
2010-12-18 00:04:26 +00:00
5e3605552e
Whitespace fixes. No functionality change.
...
llvm-svn: 122110
2010-12-17 23:27:41 +00:00
cf846100d8
Avoid dereferencing end() in collectInterferingVRegs() when there is no
...
interference.
llvm-svn: 122108
2010-12-17 23:16:38 +00:00
2e98ee31b3
Make the -verify-regalloc command line option available to base classes as
...
RegAllocBase::VerifyEnabled.
Run the machine code verifier in a few interesting places during RegAllocGreedy.
llvm-svn: 122107
2010-12-17 23:16:35 +00:00
1740e00104
Enable loop splitting in RegAllocGreedy.
...
The heuristics split around the largest loop where the current register may be
allocated without interference.
llvm-svn: 122106
2010-12-17 23:16:32 +00:00
7aa18bf46a
Add vector versions of some existing scalar transforms to aid codegen in matching psign & pblend operations to the IR produced by clang/gcc for their C idioms.
...
llvm-svn: 122105
2010-12-17 23:12:19 +00:00
3fff1fd49b
During local stack slot allocation, the materializeFrameBaseRegister function
...
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.
Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)
<rdar://problem/8782198>
llvm-svn: 122104
2010-12-17 23:09:14 +00:00
5408144add
Fix a DAGCombiner crash when folding binary vector operations with constant
...
BUILD_VECTOR operands where the element type is not legal. I had previously
changed this code to insert TRUNCATE operations, but that was just wrong.
llvm-svn: 122102
2010-12-17 23:06:49 +00:00
a7dabbd2cf
Avoid report_fatal_error in ARM's PrintAsmOperand method.
...
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.
llvm-svn: 122100
2010-12-17 23:06:42 +00:00
ec3ff9c727
Remove trailing whitespace.
...
llvm-svn: 122099
2010-12-17 23:06:32 +00:00
97b72c99d2
Add support for matching psign & plendvb to the x86 target
...
Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts
llvm-svn: 122098
2010-12-17 22:55:37 +00:00
79855298b9
Thumb's forced-PC-alignment requirement applies to the _total_ displacement, not just to the fragment relative
...
portion. While the fragment boundary is usually already aligned, it is possible for it not to be, which
would lead to a non-aligned final displacement.
llvm-svn: 122091
2010-12-17 21:49:48 +00:00
cd538afa52
Add a transform to DAG Combiner. This improves the
...
code for the case where 32-bit divide by constant is
turned into 64-bit multiply by constant. 8771012.
llvm-svn: 122090
2010-12-17 21:45:49 +00:00
559e09e39d
Support/Path: Deprecate PathV1::isAbsolute.
...
llvm-svn: 122086
2010-12-17 21:21:31 +00:00
ffa42ced39
PathV2: Use StringRef::substr to simplify substring creation.
...
llvm-svn: 122085
2010-12-17 20:27:37 +00:00
a043b62870
Allow missing kill flags on an untied operand of a two-address instruction when
...
the operand uses the same register as a tied operand:
%r1 = add %r1, %r1
If add were a three-address instruction, kill flags would be required on at
least one of the uses. Since it is a two-address instruction, the tied use
operand must not have a kill flag.
This change makes the kill flag on the untied use operand optional.
llvm-svn: 122082
2010-12-17 19:18:41 +00:00
97f1de7347
If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in with
...
a partial value. rdar://8782954
llvm-svn: 122078
2010-12-17 19:03:02 +00:00
cb520cd8cb
Missed some StringRefRefs.
...
llvm-svn: 122077
2010-12-17 18:59:09 +00:00
06ab8b648c
Add bits 31-28 to the Thumb2 encoding of TBB/TBH.
...
llvm-svn: 122076
2010-12-17 18:42:56 +00:00
4416dfa8fb
Handle 2 and 4 byte data blob fixup values for ARM.
...
llvm-svn: 122075
2010-12-17 18:39:10 +00:00
292b44baea
Pass StringRefs by value, for consistency.
...
llvm-svn: 122074
2010-12-17 18:19:06 +00:00
38b6d494d5
Add MachineLoopRange comparators for sorting loop lists by number and by area.
...
llvm-svn: 122073
2010-12-17 18:13:52 +00:00
1294ea7d53
Reapply r121905 (automatic synthesis of @llvm.sadd.with.overflow) with a fix for a bug that manifested itself
...
on the DragonEgg self-host bot. Unfortunately, the testcase is pretty messy and doesn't reduce well due to
interactions with other parts of InstCombine.
llvm-svn: 122072
2010-12-17 18:08:00 +00:00
d11460a65b
Store and free the TargetObjectWriter.
...
llvm-svn: 122070
2010-12-17 18:01:31 +00:00
6b5e56c2b1
Stub out explicit MCELFObjectTargetWriter interface.
...
llvm-svn: 122067
2010-12-17 17:45:22 +00:00
f0e24d426a
Move createELFObjectWriter to its own header.
...
llvm-svn: 122064
2010-12-17 16:59:53 +00:00
e5f49c4ff2
SimplifyCFG: Ranges can be larger than 64 bits. Fixes Release-selfhost build.
...
llvm-svn: 122054
2010-12-17 10:48:14 +00:00
a29e1bf8ad
Fix mismatched new[]/delete.
...
llvm-svn: 122053
2010-12-17 09:56:50 +00:00
affe15fd67
Don't feed 19 bit immediates to ILA.
...
Patch (slightly modified) by Visa Putkinen.
llvm-svn: 122052
2010-12-17 09:36:09 +00:00
df63335844
Use getFixupKindInfo to implement isFixupKindPCRel, ELF version.
...
llvm-svn: 122050
2010-12-17 07:28:17 +00:00
d14b0f1db7
improve switch formation to handle small range
...
comparisons formed by comparisons. For example,
this:
void foo(unsigned x) {
if (x == 0 || x == 1 || x == 3 || x == 4 || x == 6)
bar();
}
compiles into:
_foo: ## @foo
## BB#0: ## %entry
cmpl $6, %edi
ja LBB0_2
## BB#1: ## %entry
movl %edi, %eax
movl $91, %ecx
btq %rax, %rcx
jb LBB0_3
instead of:
_foo: ## @foo
## BB#0: ## %entry
cmpl $2, %edi
jb LBB0_4
## BB#1: ## %switch.early.test
cmpl $6, %edi
ja LBB0_3
## BB#2: ## %switch.early.test
movl %edi, %eax
movl $88, %ecx
btq %rax, %rcx
jb LBB0_4
This catches a bunch of cases in GCC, which look like this:
%804 = load i32* @which_alternative, align 4, !tbaa !0
%805 = icmp ult i32 %804, 2
%806 = icmp eq i32 %804, 3
%or.cond121 = or i1 %805, %806
%807 = icmp eq i32 %804, 4
%or.cond124 = or i1 %or.cond121, %807
br i1 %or.cond124, label %.thread, label %808
turning this into a range comparison.
llvm-svn: 122045
2010-12-17 06:20:15 +00:00
e054a782fc
MC/ARM: Use aggressive symbol folding (important for jump tables, for example).
...
llvm-svn: 122044
2010-12-17 06:00:24 +00:00
137d422e50
MC/Expr: Implemnt more aggressive folding during symbol evaluation using
...
IsSymbolRefDifferenceFullyResolved(). For example, we will now fold away
something like:
--
_a:
...
L0:
...
L1:
...
.long (L1 - L0) / 2
--
llvm-svn: 122043
2010-12-17 05:50:33 +00:00
2ee6c9b8c9
MC/Mach-O: On second thought, use a custom hook for enabling aggressive
...
IsSymbolRefDifferenceFullyResolved, it turns out this does change behavior on
enough cases for x86-32 that I would rather wait a bit on it.
- In practice, we will want to change this eventually because it only means we
generate less relocations (it also eliminates the need for the horrible
'.set' hack that Darwin requires in some places).
llvm-svn: 122042
2010-12-17 05:50:29 +00:00
b27bb86ba5
MC/Mach-O: Implement IsSymbolRefDifferenceFullyResolved.
...
- Unlike for fixups, we always do the "reliable" thing (not just for x86_64).
- Since Darwin 'as' would typically reject things that using this will allow,
we don't need to worry about compatibility.
llvm-svn: 122038
2010-12-17 04:54:58 +00:00
f2adf782ab
MC/ObjectWriter: Add a new IsSymbolRefDifferenceFullyResolved target format specific hook.
...
- Currently just has stub implementations for Mach-O, ELF, and COFF.
llvm-svn: 122037
2010-12-17 04:54:54 +00:00
9c7f3a46d8
Provide LiveIntervalUnion::Query::checkLoopInterference.
...
This is a three-way interval list intersection between a virtual register, a
live interval union, and a loop. It will be used to identify interference-free
loops for live range splitting.
llvm-svn: 122034
2010-12-17 04:09:47 +00:00
50269280f8
MC/Assembler: Strip out object writer arguments, now that it is always available
...
-- and remove FIXME asking for the same!
llvm-svn: 122032
2010-12-17 02:45:59 +00:00
42a037abb1
MC/Assembler: Make the MCObjectWriter available through the lifetime of the
...
assembler.
llvm-svn: 122031
2010-12-17 02:45:41 +00:00
f638b26f17
Trailing whitespace and 80 column fixups.
...
llvm-svn: 122026
2010-12-17 02:10:59 +00:00
d2867f13a0
MC/Target: Remove HasScatteredSymbols target hook variable, which has been
...
superceded and was effectively dead.
llvm-svn: 122024
2010-12-17 02:06:08 +00:00
e491ea4630
MC/Expr: Simplify.
...
llvm-svn: 122023
2010-12-17 02:05:45 +00:00
bfc6904fc6
Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.
...
Radar 8776599
llvm-svn: 122018
2010-12-17 01:21:12 +00:00
261aad8e16
Use PairDRegs to implement ConcatVectors. No functionality change.
...
llvm-svn: 122017
2010-12-17 01:21:08 +00:00
137dcdba8a
Fix a comment typo.
...
llvm-svn: 122016
2010-12-17 01:21:05 +00:00
93dc2b808f
Revert r64460. strtol and friends cannot be marked readonly, even with
...
a null endptr argument, because they may write to errno.
This fixes a seflhost miscompile observed on Linux targets when TBAA
was enabled.
llvm-svn: 122014
2010-12-17 01:09:43 +00:00
f89156da92
MC: Remove another dead MCAssembler argument, and update clients.
...
llvm-svn: 122013
2010-12-17 01:07:35 +00:00
f15aeb8d01
MC: Remove dead MCAssembler argument -- Rafael, can you check the FIXME I added
...
here?
llvm-svn: 122012
2010-12-17 01:07:31 +00:00
9af1335b5d
MC: Simplify (remove unnecessary MCAssembler argument, obsoleted by containment
...
in MCAsmLayout).
llvm-svn: 122011
2010-12-17 01:07:28 +00:00
33d571e2ae
Write => in a more normal form.
...
llvm-svn: 122009
2010-12-17 01:07:22 +00:00
76793bac89
MC/Expr: Simplify (and add a FIXME).
...
llvm-svn: 122008
2010-12-17 01:07:20 +00:00
32c74ea3ab
"Fix" FDE alignment to match what gas does.
...
llvm-svn: 122006
2010-12-17 00:28:02 +00:00
654cc4a81c
Make pushq produce signed relocations.
...
llvm-svn: 122005
2010-12-16 22:50:01 +00:00
266f4092d7
Fix MBlaze backend call instructions so that arguments passed through registers
...
are correctly marked as used. This removes a hack where the call instructions
marked all possible argument registers as used in the tablegen description.
llvm-svn: 121994
2010-12-16 19:41:31 +00:00
b5743b9d76
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
...
llvm-svn: 121990
2010-12-16 19:11:16 +00:00
395a09922b
MC/Expr: Add a doxyment.
...
llvm-svn: 121988
2010-12-16 18:36:25 +00:00
03fcccbb47
MC/Mach-O: Lift some MachObjectWriter arguments into the target specific
...
interface.
llvm-svn: 121981
2010-12-16 17:21:02 +00:00
8888a9604d
MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface.
...
llvm-svn: 121973
2010-12-16 16:09:19 +00:00
7ee218127a
Fix indentation (per style guide).
...
llvm-svn: 121972
2010-12-16 16:08:43 +00:00
73b8713d7c
MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h.
...
llvm-svn: 121971
2010-12-16 16:08:33 +00:00
9d1ed19982
MC/Mach-O: Use fixup info instead of hard coded list.
...
llvm-svn: 121970
2010-12-16 15:42:31 +00:00
9bbe849fc3
Fix a bug in the loop in JumpThreading::ProcessThreadableEdges() where it could falsely produce a MultipleDestSentinel value if the first predecessor ended with an 'indirectbr'. If that happened, it caused an unnecessary FindMostPopularDest() call.
...
This wasn't a correctness problem, but it broke the fast path for single-predecessor blocks.
llvm-svn: 121966
2010-12-16 12:16:00 +00:00
8d1ab6f6e1
Speculatively revert commit 121905 since it looks like it might have broken the
...
dragonegg self-host buildbot. Original commit message:
Add an InstCombine transform to recognize instances of manual overflow-safe addition
(performing the addition in a wider type and explicitly checking for overflow), and
fold them down to intrinsics. This currently only supports signed-addition, but could
be generalized if someone works out the magic constant formulas for other operations.
llvm-svn: 121965
2010-12-16 09:40:54 +00:00
39a0ffc394
MemoryBuffer now return an error_code and returns a OwningPtr<MemoryBuffer> via an out parm.
...
llvm-svn: 121958
2010-12-16 03:29:14 +00:00
0c9d9fdd81
MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
...
the MCCodeEmitter, which seems like a better organization.
- Also, cleaned up some magic constants while in the area.
llvm-svn: 121953
2010-12-16 03:20:06 +00:00
4c1386add9
1. ARM/MC/ELF: A few more ELF relocs for .o
...
2. Fixed EmitLocalCommonSymbol for ELF (Yes, they exist. :)
Test added.
llvm-svn: 121951
2010-12-16 03:12:17 +00:00
ecd0c8a557
MC: Make TargetAsmBackend available to the AsmStreamer.
...
- Treaty talks on the non-proliferation of MC objects broke down.
llvm-svn: 121949
2010-12-16 03:05:59 +00:00
91ab4ffd96
Update a comment.
...
llvm-svn: 121946
2010-12-16 02:55:10 +00:00
e1a17a3473
Make memcpyopt TBAA-aware.
...
llvm-svn: 121944
2010-12-16 02:51:19 +00:00
2e071faed8
lib/Support/regexec.c: Let Regex LLP64-aware.
...
On LLP64 Win64, 'states1' (for small version) was expanded to 'char *' for large version. Thus small version would be mischosen when nstates > 32 regardless of sizeof(long) on Win64.
llvm-svn: 121942
2010-12-16 01:48:15 +00:00
e9afc740a8
Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang
...
(see PR4579).
llvm-svn: 121939
2010-12-16 01:34:26 +00:00
9613a09e5c
Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
...
it. I.e., it was always an immediate value.
llvm-svn: 121932
2010-12-16 00:50:33 +00:00
637813a258
Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
...
respectively.
It may be a bug that these opcodes are getting this far into machine code
generation.
llvm-svn: 121931
2010-12-16 00:49:54 +00:00
f5b17c32d2
Add encodings for Thumb1 Spill and Restore pseudos.
...
llvm-svn: 121929
2010-12-16 00:38:41 +00:00
2c9d342f04
Enable TBAA by default.
...
llvm-svn: 121923
2010-12-15 23:58:44 +00:00
4467aa5294
Preserve TBAA tags when doing load PRE.
...
llvm-svn: 121921
2010-12-15 23:53:55 +00:00
bfef309d11
Thumb1 had two patterns for the same load-from-constant-pool instruction.
...
Canonicalize on tLDRpci and remove tLDRcp.
llvm-svn: 121920
2010-12-15 23:52:36 +00:00
347f4c32e8
Don't handle -arm-long-calls in fast isel for now.
...
llvm-svn: 121919
2010-12-15 23:47:29 +00:00
e7601e97e1
Start using SplitKit and MachineLoopRanges in RegAllocGreedy in preparation of
...
live range splitting around loops guided by register pressure.
So far, trySplit() simply prints a lot of debug output.
llvm-svn: 121918
2010-12-15 23:46:13 +00:00
5e97781386
Add MachineLoopRanges analysis.
...
A MachineLoopRange contains the intervals of slot indexes covered by the blocks
in a loop. This representation of the loop blocks is more efficient to compare
against interfering registers during register coalescing.
llvm-svn: 121917
2010-12-15 23:41:23 +00:00
7d3bde98f1
If we're changing the frame register to a physical register other than SP, we
...
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.
llvm-svn: 121915
2010-12-15 23:32:27 +00:00
6217ecd634
Whitespace cleanups.
...
llvm-svn: 121914
2010-12-15 23:31:24 +00:00
f991d4f587
Better fix for opt build
...
llvm-svn: 121910
2010-12-15 23:14:45 +00:00
be69d8e2f3
Only rr forms of ADD*_DB are commutable.
...
llvm-svn: 121908
2010-12-15 22:57:36 +00:00
1cf8881299
Add an InstCombine transform to recognize instances of manual overflow-safe addition
...
(performing the addition in a wider type and explicitly checking for overflow), and
fold them down to intrinsics. This currently only supports signed-addition, but could
be generalized if someone works out the magic constant formulas for other operations.
Fixes <rdar://problem/8558713>.
llvm-svn: 121905
2010-12-15 22:32:38 +00:00
15f96baa01
Fix opt -Werror build
...
llvm-svn: 121904
2010-12-15 22:21:20 +00:00
b7ff5a0f20
Teach machine cse to commute instructions.
...
llvm-svn: 121903
2010-12-15 22:16:21 +00:00
fa27a8621c
Add Neon VCVT instructions for f32 <-> f16 conversions.
...
Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
llvm-svn: 121902
2010-12-15 22:14:12 +00:00
05b18f143f
Reapply r121886, and also update DecomposeGEPExpression to keep
...
it in sync.
llvm-svn: 121895
2010-12-15 20:49:55 +00:00
d02b65982e
Revert r121886. DecomposeGEPExpression needs to be kept
...
in sync.
llvm-svn: 121892
2010-12-15 20:39:25 +00:00
0c558b2080
Lower the MBlaze target specific calling conventions for "interrupt_handler"
...
and "save_volatiles" correctly. This completes the custom calling convention
functionality changes for the MBlaze backend that were started in 121888.
llvm-svn: 121891
2010-12-15 20:27:28 +00:00
949ab7889c
Strengthen GetUnderlyingObject using InstructionSimplify.
...
While LLVM's main design is that analysis code shouldn't
go out of its way to understand code which hasn't been
InstCombined, analysis utility routines like this can
find themselves being called in the middle of transform
passes when instcombine hasn't had a chance to run.
llvm-svn: 121886
2010-12-15 20:10:26 +00:00
a4fcd2418d
Move Value::getUnderlyingObject to be a standalone
...
function so that it can live in Analysis instead of
VMCore.
llvm-svn: 121885
2010-12-15 20:02:24 +00:00
fdb174b6ef
Add some special purpose register definitions to the MBlaze backend and cleanup some old, unused floating point register definitions.
...
llvm-svn: 121882
2010-12-15 19:35:36 +00:00
c8fa5fcc42
Fix typo in r121875.
...
llvm-svn: 121880
2010-12-15 19:24:24 +00:00
23477c2ee5
Tweak a few pseudo-inst pattern base classes.
...
llvm-svn: 121878
2010-12-15 19:03:16 +00:00
11678bd299
Clean up some of LVI:
...
* mergeIn now uses constant folding for constants that are provably not-equal.
* sink some sanity checks from the get*() methods into the mark*() methods, to ensure that we never have a constant/notconstant ConstantInt
* some textual cleanups, whitespace changes, removing "else" after return, that sort of thing.
llvm-svn: 121877
2010-12-15 18:57:18 +00:00
d42257ceef
The new t2LEApcrel* pseudo instructions need the size specified.
...
rdar://8768390
llvm-svn: 121876
2010-12-15 18:48:45 +00:00
622ad5170b
Implement cleanups suggested by Daniel.
...
llvm-svn: 121875
2010-12-15 18:48:27 +00:00
1066ef6b24
Fix build.
...
llvm-svn: 121872
2010-12-15 18:07:48 +00:00
28e769cc54
Detect and enumerate bypass loops.
...
Bypass loops have the current live range live through, but contain no uses or
defs. Splitting around a bypass loop can free registers for other uses inside
the loop by spilling the split range.
llvm-svn: 121871
2010-12-15 17:49:52 +00:00
4391f34aba
Separate SplitAnalysis::getSplitLoops().
...
This method returns the set of loops with uses that are candidates for
splitting.
llvm-svn: 121870
2010-12-15 17:41:19 +00:00
0a2c416894
Move Sub simplifications and additional Add simplifications out of
...
instcombine and into InstructionSimplify.
llvm-svn: 121861
2010-12-15 14:07:39 +00:00
019a418808
If we detect that the instruction we are simplifying is unreachable, arrange for
...
it to be replaced by undef rather than not replaced at all, the idea being that
this may reduce the amount of work done by whoever called InstructionSimplify.
llvm-svn: 121860
2010-12-15 11:02:22 +00:00
3d1803495e
Teach jump threading to "look through" a select when the branch direction of a terminator depends on it.
...
When it sees a promising select it now tries to figure out whether the condition of the select is known in any of the predecessors and if so it maps the operands appropriately.
llvm-svn: 121859
2010-12-15 09:51:20 +00:00
03e7576dee
Add fixups for Thumb LDR/STR instructions.
...
llvm-svn: 121858
2010-12-15 08:51:02 +00:00
844f6b6cfb
Relax alignment fragments.
...
With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).
This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.
llvm-svn: 121857
2010-12-15 08:45:53 +00:00
8911d03504
Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments.
...
Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.
llvm-svn: 121856
2010-12-15 07:39:29 +00:00
5174921b5b
add another overflow idiom
...
llvm-svn: 121854
2010-12-15 07:28:58 +00:00
2e33985300
add a note about overflow idiom recognition.
...
llvm-svn: 121853
2010-12-15 07:25:55 +00:00
f80f18a11a
Generalize an assert.
...
llvm-svn: 121851
2010-12-15 07:12:24 +00:00
27ecda1efd
add a shift/imul missed optimization
...
llvm-svn: 121850
2010-12-15 07:10:43 +00:00
aded09f27f
add a note about a SPEC hack that gcc mainline does.
...
llvm-svn: 121849
2010-12-15 06:38:24 +00:00
15090e1eb0
take care of some todos, transforming [us]mul_lohi into
...
a wider mul if the wider mul is legal.
llvm-svn: 121848
2010-12-15 06:04:19 +00:00
b86dceea1b
when transforming a MULHS into a wider MUL, there is no need to SRA the
...
result, the top bits are truncated off anyway, just use SRL.
llvm-svn: 121846
2010-12-15 05:51:39 +00:00
e893e2601e
make qsort predicate more conformant by returning 0 for equal values.
...
llvm-svn: 121838
2010-12-15 04:52:41 +00:00
832a5daab5
Reapply r121808 now that the missing patterns have been supplied.
...
llvm-svn: 121820
2010-12-15 01:03:19 +00:00
1171e9e81d
Add some missing patterns now that tLDRB and tLDRH are split into reg and
...
immediate versions.
llvm-svn: 121819
2010-12-15 00:58:57 +00:00
35609d97ae
Fix PR8790, another instance where unreachable code can cause instruction simplification to fail,
...
this case involve a select that simplifies to itself.
llvm-svn: 121817
2010-12-15 00:55:35 +00:00
15c85c916f
Cleanup trailing whitespace.
...
llvm-svn: 121816
2010-12-15 00:52:44 +00:00
20480d26e9
Revert r121808 until I can fix the build.
...
llvm-svn: 121815
2010-12-15 00:04:00 +00:00
eda5177ca6
thumb adr fixup needs alignment just like the t2 version.
...
llvm-svn: 121812
2010-12-14 23:47:35 +00:00
5ab38b59e6
Comments and cleaning.
...
llvm-svn: 121809
2010-12-14 23:42:48 +00:00
00adcd6ed9
Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
...
particular, we want
ldr r2, [r3]
to be equivalent to
ldr r2, [r3, #0 ]
and not
ldr r2, [r3, r0]
llvm-svn: 121808
2010-12-14 23:40:49 +00:00
0b7ca3a6a7
Simplify RegAllocGreedy's use of register aliases.
...
llvm-svn: 121807
2010-12-14 23:38:19 +00:00
47b93401d8
Simplify CCState's use of register aliases.
...
llvm-svn: 121806
2010-12-14 23:28:01 +00:00
be1c8d3a82
Simplify AggressiveAntiDepBreaker's use of register aliases.
...
llvm-svn: 121805
2010-12-14 23:23:15 +00:00
6a5bf7782a
Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet.
...
llvm-svn: 121801
2010-12-14 23:10:48 +00:00
509dc2a700
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
...
llvm-svn: 121798
2010-12-14 22:28:03 +00:00
6ea3053824
Fix comment.
...
llvm-svn: 121797
2010-12-14 22:26:49 +00:00
ce4f87b3ba
Multiclassify the LDR/STR encoding patterns. The only functionality difference
...
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
llvm-svn: 121794
2010-12-14 22:10:49 +00:00
19dc77cec6
Fix a minor bug in two-address pass. It was missing a commute opportunity.
...
regB = move RCX
regA = op regB, regC
RAX = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
movl %edi, %eax
shlq $32, %rcx
leaq (%rcx,%rax), %rax
=>
movl %edi, %eax
shlq $32, %rcx
orq %rcx, %rax
rdar://8762995
llvm-svn: 121793
2010-12-14 21:34:53 +00:00
d96bd53d04
trailing whitespace
...
llvm-svn: 121792
2010-12-14 21:28:29 +00:00
86a05d0bed
Move debugging code entirely within DEBUG(). Silences an unused variable
...
warning in the opt build.
llvm-svn: 121791
2010-12-14 21:14:55 +00:00
8c1fabe367
Refactor a bit for legibility.
...
llvm-svn: 121790
2010-12-14 21:10:47 +00:00
2fc6561102
trailing whitespace.
...
llvm-svn: 121789
2010-12-14 20:46:39 +00:00
96254146cf
Make sure to propagate the predicate operands for LEApcrel to ADR.
...
llvm-svn: 121788
2010-12-14 20:45:47 +00:00
f636a64bfe
Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.
...
llvm-svn: 121784
2010-12-14 19:42:53 +00:00
5c3ad0d51e
Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew.
...
llvm-svn: 121783
2010-12-14 19:38:49 +00:00
d5e38383e0
Use TRI::printReg instead of AbstractRegisterDescription when printing
...
LiveIntervalUnions.
llvm-svn: 121781
2010-12-14 18:53:47 +00:00
2dd1ee5fd5
Add TargetRegisterInfo::printReg() to pretty-print registers.
...
llvm-svn: 121780
2010-12-14 18:53:39 +00:00
41955ff958
ARM Fixups relative to thumb functions need to have the low bit of the value
...
set for interworking to work properly. rdar://8755956
llvm-svn: 121778
2010-12-14 18:46:57 +00:00
e7ee72087e
Q.seenAllInterferences() must be called after Q.collectInterferingVRegs().
...
llvm-svn: 121774
2010-12-14 17:47:36 +00:00
a9b9300bb8
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
...
llvm-svn: 121772
2010-12-14 17:37:16 +00:00
e34793e960
Trailing whitespace
...
llvm-svn: 121769
2010-12-14 16:25:15 +00:00
6dd0c07622
Use the integer scheduling intrinsic for integer loads and stores.
...
llvm-svn: 121765
2010-12-14 12:33:05 +00:00
7499b452c1
- Insert new instructions before DomBlock's terminator,
...
which is simpler than finding a place to insert in BB.
- Don't perform the 'if condition hoisting' xform on certain
i1 PHIs, as it interferes with switch formation.
This re-fixes "example 7", without breaking the world hopefully.
llvm-svn: 121764
2010-12-14 08:46:09 +00:00
335f0e4ad4
fix two significant issues with FoldTwoEntryPHINode:
...
first, it can kick in on blocks whose conditions have been
folded to a constant, even though one of the edges will be
trivially folded.
second, it doesn't clean up the "if diamond" that it just
eliminated away. This is a problem because other simplifycfg
xforms kick in depending on the order of block visitation,
causing pointless work.
llvm-svn: 121762
2010-12-14 08:01:53 +00:00
dc20a7d38c
remove the instsimplify logic I added in r121754. It is apparently
...
breaking the selfhost builds, though I can't fathom how.
llvm-svn: 121761
2010-12-14 07:53:03 +00:00
9ac168d0ab
clean up logic, convert std::set to SmallPtrSet, handle the case
...
when all 2-entry phis are simplified away.
llvm-svn: 121760
2010-12-14 07:41:39 +00:00
9fd838d31b
tidy up a bit, move DEBUG down to when we commit to doing the transform so we
...
don't print it unless the xform happens.
llvm-svn: 121758
2010-12-14 07:23:10 +00:00
b42d293faa
use SimplifyInstruction instead of reimplementing part of it.
...
llvm-svn: 121757
2010-12-14 07:20:29 +00:00
fb73de482c
simplify GetIfCondition by using getSinglePredecessor.
...
llvm-svn: 121756
2010-12-14 07:15:21 +00:00
0f4d67bd88
use AddPredecessorToBlock in 3 places instead of a manual loop.
...
llvm-svn: 121755
2010-12-14 07:09:42 +00:00
a07cc6f4fd
make FoldTwoEntryPHINode use instsimplify a bit, make
...
GetIfCondition faster by avoiding pred_iterator. No
really interesting change.
llvm-svn: 121754
2010-12-14 07:00:00 +00:00
afd2a8cfbb
remove the dead (and terrible) llvm::RemoveSuccessor function.
...
llvm-svn: 121753
2010-12-14 06:51:55 +00:00
d7beca3782
improve DEBUG's a bit, switch to eraseFromParent() to simplify
...
code a bit, switch from constant folding to instsimplify.
llvm-svn: 121751
2010-12-14 06:17:25 +00:00
5a9d59d918
reapply my recent change that disables a piece of the switch formation
...
work, but fixes 400.perlbmk.
llvm-svn: 121749
2010-12-14 05:57:30 +00:00
092a7bdf9f
The tLDR et al instructions were emitting either a reg/reg or reg/imm
...
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
2010-12-14 03:36:38 +00:00
c177813755
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663
...
llvm-svn: 121746
2010-12-14 03:22:07 +00:00
eba9095df2
Remove unused vector.
...
llvm-svn: 121741
2010-12-14 00:58:47 +00:00
903b6d3261
Try reassigning all virtual register interferences, not just those with lower
...
spill weight. Filter out fixed registers instead.
Add support for reassigning an interference that was assigned to an alias.
llvm-svn: 121737
2010-12-14 00:37:49 +00:00
3d7b8066aa
Add stub for RAGreedy::trySplit.
...
llvm-svn: 121736
2010-12-14 00:37:44 +00:00
6d375e5637
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
...
process cleaner.
llvm-svn: 121735
2010-12-14 00:36:49 +00:00
3e5648896e
Fix recent buildbot breakage by pulling SimplifyCFG back to its state as of r121694, the most recent state
...
where I'm confident there were no crashes or miscompilations. XFAIL the test added since then for now.
llvm-svn: 121733
2010-12-13 23:49:28 +00:00
0e909c5f9c
First cut of ARM/MC/ELF PIC relocations.
...
Test has fixme, to move to .s -> .o test when AsmParser works better.
llvm-svn: 121732
2010-12-13 23:16:07 +00:00
651eaa02b8
Remove the rest of the *_sfp Neon instruction patterns.
...
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
llvm-svn: 121730
2010-12-13 23:02:37 +00:00
aae0862172
Simplify N2VSPat, removing some unnecessary type arguments.
...
llvm-svn: 121729
2010-12-13 23:02:31 +00:00
a6e5d5694a
temporarily disable part of my previous patch, which causes an iterator invalidation issue, causing a crash on some versions of perlbmk.
...
llvm-svn: 121728
2010-12-13 23:02:19 +00:00
3cb55a1d23
Update a comment.
...
llvm-svn: 121727
2010-12-13 22:53:18 +00:00
9a4d42855d
Revert r121721, which broke buildbots.
...
llvm-svn: 121726
2010-12-13 22:51:08 +00:00
c4bf5cac9f
Reapply r121520, PartialAlias implementation for BasicAA, now that
...
memdep is updated to handle it.
llvm-svn: 121725
2010-12-13 22:50:24 +00:00
ba5d0abe39
Update memdep to handle PartialAlias as MayAlias.
...
llvm-svn: 121723
2010-12-13 22:47:57 +00:00
4efa445f3c
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
...
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
llvm-svn: 121721
2010-12-13 22:29:52 +00:00
9c00c014ab
Delete a line that I forgot to revert previously.
...
llvm-svn: 121719
2010-12-13 22:05:55 +00:00
9b3546d877
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
...
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns. The pattern
gets pretty ugly but it seems to work well. Partial fix for Radar 8711675.
llvm-svn: 121718
2010-12-13 21:58:05 +00:00
157fec42c9
Use pseudo instructions for 2-register Neon instructions for scalar FP.
...
Partial fix for Radar 8711675.
llvm-svn: 121716
2010-12-13 21:05:52 +00:00
52f522720e
Remove unused instruction class arguments.
...
llvm-svn: 121715
2010-12-13 21:05:44 +00:00
2e51bb4ff0
Generalize BFI isel lowering a bit.
...
llvm-svn: 121714
2010-12-13 20:32:54 +00:00
2d434e594e
add some DEBUG's.
...
llvm-svn: 121711
2010-12-13 19:55:30 +00:00
578074b2f3
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
...
as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
llvm-svn: 121710
2010-12-13 19:31:11 +00:00
f588c516b7
Use 32-bit types for 32-bit values.
...
llvm-svn: 121709
2010-12-13 19:25:46 +00:00
3aeb867d74
Trailing whitespace.
...
llvm-svn: 121708
2010-12-13 19:18:13 +00:00
1e155ab7e1
Fix sort predicate. qsort(3)'s predicate semantics differ from std::sort's. Fixes PR 8780.
...
llvm-svn: 121705
2010-12-13 18:20:38 +00:00
10bd29f1d4
Add a couple dag combines to transform mulhi/mullo into a wider multiply
...
when the wider type is legal. This allows us to compile:
define zeroext i16 @test1(i16 zeroext %x) nounwind {
entry:
%div = udiv i16 %x, 33
ret i16 %div
}
into:
test1: # @test1
movzwl 4(%esp), %eax
imull $63551, %eax, %eax # imm = 0xF83F
shrl $21, %eax
ret
instead of:
test1: # @test1
movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F
mulw 4(%esp)
andl $65504, %edx # imm = 0xFFE0
movl %edx, %eax
shrl $5, %eax
ret
Implementing rdar://8760399 and example #4 from:
http://blog.regehr.org/archives/320
We should implement the same thing for [su]mul_hilo, but I don't
have immediate plans to do this.
llvm-svn: 121696
2010-12-13 08:39:01 +00:00
fb836f8c1a
reinstate my patch: the miscompile was caused by an inverted branch in the
...
'and' case.
llvm-svn: 121695
2010-12-13 08:12:19 +00:00
79db357d80
Completely disable the optimization I added in r121680 until
...
I can track down a miscompile. This should bring the buildbots
back to life
llvm-svn: 121693
2010-12-13 07:41:29 +00:00
f8d180b808
remove the verbose-asm "constant pool double" comments that we were printing
...
for each constant pool entry. Using WriteTypeSymbolic here takes time
proportional to the size of the module, for each constant pool entry.
This speeds up -verbose-asm llc on 252.eon (a random testcase at my disposal)
from 4.4s to 2.137s. llc takes 2.11s with asm-verbose off, so this is now a
pretty reasonable cost for verbose comments.
llvm-svn: 121691
2010-12-13 07:35:47 +00:00
fbeb55844b
Make simplifycfg reprocess newly formed "br (cond1 | cond2)" conditions
...
when simplifying, allowing them to be eagerly turned into switches. This
is the last step required to get "Example 7" from this blog post:
http://blog.regehr.org/archives/320
On X86, we now generate this machine code, which (to my eye) seems better
than the ICC generated code:
_crud: ## @crud
## BB#0: ## %entry
cmpb $33, %dil
jb LBB0_4
## BB#1: ## %switch.early.test
addb $-34, %dil
cmpb $58, %dil
ja LBB0_3
## BB#2: ## %switch.early.test
movzbl %dil, %eax
movabsq $288230376537592865, %rcx ## imm = 0x400000017001421
btq %rax, %rcx
jb LBB0_4
LBB0_3: ## %lor.rhs
xorl %eax, %eax
ret
LBB0_4: ## %lor.end
movl $1, %eax
ret
llvm-svn: 121690
2010-12-13 07:00:06 +00:00
1d05761df4
make this logic a bit simpler.
...
llvm-svn: 121689
2010-12-13 06:36:51 +00:00
25c3af35d8
split all the guts of SimplifyCFGOpt::run out into one function
...
per terminator kind.
llvm-svn: 121688
2010-12-13 06:25:44 +00:00
cb570f87e5
fix a bug in r121680 that upset the various buildbots.
...
llvm-svn: 121687
2010-12-13 05:34:18 +00:00
a6db741f3d
refactor the speculative execution logic to be factored into the cond branch code instead of
...
doing a cfg search for every block simplified.
llvm-svn: 121686
2010-12-13 05:26:52 +00:00
466f54ffcf
simplify a bunch of code.
...
llvm-svn: 121685
2010-12-13 05:20:28 +00:00
6df7bdd810
move HoistThenElseCodeToIf up to a more logical and efficient-to-handle place.
...
llvm-svn: 121684
2010-12-13 05:15:29 +00:00
2e3832d9a0
move 'MergeBlocksIntoPredecessor' call earlier. Use
...
getSinglePredecessor to simplify code.
llvm-svn: 121683
2010-12-13 05:10:48 +00:00
a69c443459
factor new code out to a SimplifyBranchOnICmpChain helper function.
...
llvm-svn: 121681
2010-12-13 05:03:41 +00:00
a442f24a36
enhance the "change or icmp's into switch" xform to handle one value in an
...
'or sequence' that it doesn't understand. This allows us to optimize
something insane like this:
int crud (unsigned char c, unsigned x)
{
if(((((((((( (int) c <= 32 ||
(int) c == 46) || (int) c == 44)
|| (int) c == 58) || (int) c == 59) || (int) c == 60)
|| (int) c == 62) || (int) c == 34) || (int) c == 92)
|| (int) c == 39) != 0)
foo();
}
into:
define i32 @crud(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
entry:
%cmp = icmp ult i8 %c, 33
br i1 %cmp, label %if.then, label %switch.early.test
switch.early.test: ; preds = %entry
switch i8 %c, label %if.end [
i8 39, label %if.then
i8 44, label %if.then
i8 58, label %if.then
i8 59, label %if.then
i8 60, label %if.then
i8 62, label %if.then
i8 46, label %if.then
i8 92, label %if.then
i8 34, label %if.then
]
by pulling the < comparison out ahead of the newly formed switch.
llvm-svn: 121680
2010-12-13 04:50:38 +00:00
5a177e681e
merge two very similar functions into one that has a bool argument.
...
llvm-svn: 121678
2010-12-13 04:26:26 +00:00
f8b4c0035b
Disable auto-detection of AVX support since AVX codegen support is not ready.
...
llvm-svn: 121677
2010-12-13 04:23:53 +00:00
9b1af510cb
don't bother handling non-canonical icmp's
...
llvm-svn: 121676
2010-12-13 04:18:32 +00:00
395252d93e
inline a function, making the result much simpler.
...
llvm-svn: 121675
2010-12-13 04:15:19 +00:00
62cc76e9cc
Fix my previous patch to handle a degenerate case that the llvm-gcc
...
bootstrap buildbot tripped over.
llvm-svn: 121674
2010-12-13 03:43:57 +00:00
11dafaa3ec
convert some methods to be static functions
...
llvm-svn: 121673
2010-12-13 03:30:12 +00:00
4642d79fb0
zap two more std::sorts.
...
llvm-svn: 121672
2010-12-13 03:24:30 +00:00
d9bacc088a
fix a fairly serious oversight with switch formation from
...
or'd conditions. Previously we'd compile something like this:
int crud (unsigned char c) {
return c == 62 || c == 34 || c == 92;
}
into:
switch i8 %c, label %lor.rhs [
i8 62, label %lor.end
i8 34, label %lor.end
]
lor.rhs: ; preds = %entry
%cmp8 = icmp eq i8 %c, 92
br label %lor.end
lor.end: ; preds = %entry, %entry, %lor.rhs
%0 = phi i1 [ true, %entry ], [ %cmp8, %lor.rhs ], [ true, %entry ]
%lor.ext = zext i1 %0 to i32
ret i32 %lor.ext
which failed to merge the compare-with-92 into the switch. With this patch
we simplify this all the way to:
switch i8 %c, label %lor.rhs [
i8 62, label %lor.end
i8 34, label %lor.end
i8 92, label %lor.end
]
lor.rhs: ; preds = %entry
br label %lor.end
lor.end: ; preds = %entry, %entry, %entry, %lor.rhs
%0 = phi i1 [ true, %entry ], [ false, %lor.rhs ], [ true, %entry ], [ true, %entry ]
%lor.ext = zext i1 %0 to i32
ret i32 %lor.ext
which is much better for codegen's switch lowering stuff. This kicks in 33 times
on 176.gcc (for example) cutting 103 instructions off the generated code.
llvm-svn: 121671
2010-12-13 03:18:54 +00:00
73a58627c3
simplify code and reduce indentation
...
llvm-svn: 121670
2010-12-13 02:38:13 +00:00
7c8e6047d6
convert an std::sort to array_pod_sort.
...
llvm-svn: 121669
2010-12-13 02:00:58 +00:00
1475987634
move the "br (X == 0 | X == 1), T, F" -> switch optimization to a new
...
location in simplifycfg. In the old days, SimplifyCFG was never run on
the entry block, so we had to scan over all preds of the BB passed into
simplifycfg to do this xform, now we can just check blocks ending with
a condbranch. This avoids a scan over all preds of every simplified
block, which should be a significant compile-time perf win on functions
with lots of edges. No functionality change.
llvm-svn: 121668
2010-12-13 01:57:34 +00:00
4088e2b8e4
reduce indentation and generally simplify code, no functionality change.
...
llvm-svn: 121667
2010-12-13 01:47:07 +00:00
7cb7867d7a
use getFirstNonPHIOrDbg to simplify this code.
...
llvm-svn: 121664
2010-12-13 01:28:06 +00:00
cb404360ca
reduce indentation by using continue, no functionality change.
...
llvm-svn: 121662
2010-12-13 01:11:17 +00:00
14cb11ddb2
add a note
...
llvm-svn: 121656
2010-12-13 00:15:25 +00:00
b4f896ce90
Missed some ADDI <-> ADDIK conversions in 121649.
...
llvm-svn: 121652
2010-12-12 22:53:14 +00:00
7d99b5b651
MBlaze delay slot filler was not capable of using ADDK and variants to fill delay slots. This broke several test cases when 121649 was committed. This fixes the regression.
...
llvm-svn: 121650
2010-12-12 22:22:49 +00:00
632b5926d3
The ADD and ADDK (and all variants) instructions where flip-flopped in the MBlaze backend. This bug fix makes 64-bit math work on the MBlaze backend.
...
llvm-svn: 121649
2010-12-12 22:02:31 +00:00
f3e1ada522
Remove useless dynamic_cast<>().
...
Thanks Peter for pointing me to something that should have never been
committed to the llvm code base.
llvm-svn: 121648
2010-12-12 21:58:28 +00:00
968bc26a0a
1. Change MBlaze indirect branches to use absolute branch BRALD instead of pc relative branch BRLD.
...
2. Make sure that the MBlaze stack is aligned to 4-byte boundaries.
3. Determine frame indexes that should be placed in the callers stack frame, as per the MBlaze ABI, and place them in the correct locations.
llvm-svn: 121639
2010-12-12 20:52:31 +00:00
d2e70b5442
Catch attempts to remove a deleted node from the CSE maps. Better to
...
catch this here rather than later after accessing uninitialized memory
etc. Fires when compiling the testcase in PR8237.
llvm-svn: 121635
2010-12-12 13:22:50 +00:00
c4169cebe3
Generalize the and-icmp-select instcombine further by allowing selects of the form
...
(x & 2^n) ? 2^m+C : C
we can offset both arms by C to get the "(x & 2^n) ? 2^m : 0" form, optimize the
select to a shift and apply the offset afterwards.
llvm-svn: 121609
2010-12-11 10:49:22 +00:00
c8b035d006
Factor the (x & 2^n) ? 2^m : 0 instcombine into its own method and generalize it
...
to catch cases where n != m with a shift.
llvm-svn: 121608
2010-12-11 09:42:59 +00:00
3434575704
(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056
...
llvm-svn: 121606
2010-12-11 04:11:38 +00:00
92da705261
Add named timer groups for the different stages of register allocation.
...
llvm-svn: 121604
2010-12-11 00:19:56 +00:00
8de03d222f
Move MRI into RegAllocBase. Clean up debug output a bit.
...
llvm-svn: 121599
2010-12-10 23:49:00 +00:00
Chris Lattner