6186c96765
When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low
...
bits are zero, not that the current low bits are zero. Fixes <rdar://problem/8606771>.
llvm-svn: 117953
2010-11-01 21:08:20 +00:00
c6627eec13
When we look at instructions to convert to setting the 's' flag, we need to look
...
at more than those which define CPSR. You can have this situation:
(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...
We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:
(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...
We cannot convert (1) to "subs" because of the intervening use of CPSR.
llvm-svn: 117950
2010-11-01 20:41:43 +00:00
cd9da22f68
Use ARM-style comment syntax.
...
llvm-svn: 117941
2010-11-01 18:33:37 +00:00
44be217af1
NEON does not support truncating vector stores. Radar 8598391.
...
llvm-svn: 117940
2010-11-01 18:31:39 +00:00
083ddf7d6a
Covert this test to .s form.
...
llvm-svn: 117939
2010-11-01 18:30:39 +00:00
a7d985738c
Convert this test to .s form.
...
llvm-svn: 117938
2010-11-01 18:26:43 +00:00
e5271a935a
Covert this test to .s form.
...
llvm-svn: 117937
2010-11-01 18:13:11 +00:00
051b7893dd
Covert this test to .s form.
...
llvm-svn: 117935
2010-11-01 18:03:16 +00:00
55ebc962ab
Fix test.
...
llvm-svn: 117932
2010-11-01 17:10:53 +00:00
13ddd6d410
Write the line info to .debug_line.
...
llvm-svn: 117930
2010-11-01 17:07:14 +00:00
0190a649e8
Mark ARM subtarget features that are available for the assembler.
...
llvm-svn: 117929
2010-11-01 16:59:54 +00:00
144fb8af58
Add support for .value.
...
llvm-svn: 117922
2010-11-01 15:29:07 +00:00
1614597873
Implement .weakref.
...
llvm-svn: 117911
2010-11-01 14:28:48 +00:00
359dd0c6bd
More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the
...
peephole optimizer is disabled. That's not good at all.
llvm-svn: 117905
2010-11-01 05:59:43 +00:00
cd4750cb4d
Disable because peephole is disabled.
...
llvm-svn: 117903
2010-11-01 05:48:44 +00:00
1acd6b1edc
"mov[zs]x (mem), GR16" are not ambiguous: the mem
...
must be 8 bits. Support this memory form.
llvm-svn: 117902
2010-11-01 05:41:10 +00:00
dd3b09c234
Implement enough of the missing instalias support to get
...
aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
llvm-svn: 117901
2010-11-01 05:34:34 +00:00
fccb9d032f
Convert this test to .s form.
...
llvm-svn: 117900
2010-11-01 05:23:58 +00:00
178f4bb62d
make the asm matcher emitter reject instructions that have comments
...
in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
llvm-svn: 117897
2010-11-01 04:44:29 +00:00
4d9f157203
fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
...
for shl. Caught by inspection.
llvm-svn: 117820
2010-10-30 18:13:10 +00:00
e490b5c29e
add a test for the ud2a alias.
...
llvm-svn: 117803
2010-10-30 17:01:25 +00:00
b8f3b14dfb
If a function does a volatile load from a global constant, do not
...
consider it to be readonly. In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment). This fixes PR8279.
llvm-svn: 117783
2010-10-30 12:59:44 +00:00
7ed597149b
Overhaul memory barriers in the ARM backend. Radar 8601999.
...
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
llvm-svn: 117756
2010-10-30 00:54:37 +00:00
193961bb1a
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
...
conditional. Check for those instructions explicitly.
llvm-svn: 117747
2010-10-29 23:50:21 +00:00
2b3f25e031
Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857.
...
llvm-svn: 117745
2010-10-29 23:36:03 +00:00
45834a0065
Be more strict on when we produce an undefined reference. In gas a file with
...
just
.type foo,@object
will produce an undefined reference to foo. On the other hand, a file with
just
.weakref bar, foo
will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.
With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.
This is in preparation for a patch implementing .weakref.
llvm-svn: 117735
2010-10-29 23:09:31 +00:00
11ee456e23
Change instcombine's getShuffleMask to represent undef with negative values.
...
This code had previously used 2*N, where N is the mask length, to represent
undef. That is not safe because the shufflevector operands may have more
than N elements -- they don't have to match the result type.
llvm-svn: 117721
2010-10-29 22:03:05 +00:00
08882be86c
Remove DAG combiner patch to fold vector splats. Instcombiner does it now.
...
llvm-svn: 117720
2010-10-29 22:03:02 +00:00
cb11b48e7a
Make instcombine a little more aggressive in combining vector shuffles.
...
Allow splats even if they don't match either of the original shuffles,
possibly due to undef entries in the shuffles masks. Radar 8597790.
Also fix some 80-column violations.
llvm-svn: 117719
2010-10-29 22:02:50 +00:00
8e7b73743d
Update testcase since we're no longer doing the constant forwarding inline with correlated value propagation.
...
llvm-svn: 117712
2010-10-29 21:18:23 +00:00
72dfc6a7c7
Convert this test to .s form.
...
llvm-svn: 117708
2010-10-29 20:39:19 +00:00
665b9e37ff
Convert this test to .s form.
...
llvm-svn: 117704
2010-10-29 20:23:45 +00:00
fe4b52a066
Convert this test to .s form.
...
llvm-svn: 117699
2010-10-29 20:17:07 +00:00
0093f9a634
Convert this test to .s form.
...
llvm-svn: 117696
2010-10-29 20:12:34 +00:00
ede9d861db
Covert this test to .s form.
...
llvm-svn: 117694
2010-10-29 19:56:07 +00:00
6f9cd06ff9
Convert this test to .s form.
...
llvm-svn: 117693
2010-10-29 19:51:11 +00:00
3ad831ac77
Convert this test to .s form.
...
llvm-svn: 117690
2010-10-29 19:45:32 +00:00
302596e5e1
Convert this test to .s form.
...
llvm-svn: 117689
2010-10-29 19:37:05 +00:00
efdf57afdc
Convert this test to .s form.
...
llvm-svn: 117686
2010-10-29 19:17:08 +00:00
221b524fe1
Convert this test to .s form.
...
llvm-svn: 117685
2010-10-29 19:09:08 +00:00
b916206545
Covert this test to .s form.
...
llvm-svn: 117684
2010-10-29 19:05:26 +00:00
733d1b1a60
Convert this test to .s form.
...
llvm-svn: 117683
2010-10-29 18:58:30 +00:00
7d23a78188
Convert this test to .s form.
...
llvm-svn: 117682
2010-10-29 18:48:59 +00:00
7eed15242d
Convert this file to less fragile .s form.
...
llvm-svn: 117681
2010-10-29 18:41:40 +00:00
13ff53e7b6
Replace this test with the less fragile .s version. Still XFAIL'd, since the ASM parser doesn't parse vabal yet.
...
llvm-svn: 117679
2010-10-29 18:31:26 +00:00
66aa87021c
Covert this test to a .s file to reduce fragility.
...
llvm-svn: 117676
2010-10-29 18:18:40 +00:00
6c1414f9c2
Avoiding overly aggressive latency scheduling. If the two nodes share an
...
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
llvm-svn: 117675
2010-10-29 18:09:28 +00:00
821de3d161
test/Scripts/macho-dump: Make hack for Python-2.4. [PR7995]
...
With Python-2.4, Reader::read64 always returns (unexpected) long integer.
FileCheck detects failure on test/MC/MachO among '0' and '0L'.
CentOS5(aka RHEL5 clone) provides python-2.4.
llvm-svn: 117637
2010-10-29 01:14:16 +00:00
15a43965ac
Teach memdep to use pointsToConstantMemory to determine that loads
...
from constant memory don't alias any stores.
llvm-svn: 117636
2010-10-29 01:14:04 +00:00
b101af04b4
Convert this test to a .s file, so that it's not sensitive to codegen changes.
...
llvm-svn: 117633
2010-10-29 01:01:56 +00:00
c16d9afe04
Add a basic testcase for TBAA-aware DSE.
...
llvm-svn: 117632
2010-10-29 00:54:02 +00:00
5d6f6a061b
add simple support for addrmode5 operands, allowing
...
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
llvm-svn: 117626
2010-10-29 00:27:31 +00:00
fc1b990b1d
The ARM jit cannot handle these tests as of 2010-10-27.
...
(A PR will be linked to this rev.)
llvm-svn: 117620
2010-10-29 00:23:43 +00:00
8aefb66376
Improvements to .section parsing:
...
* If we have a M or a G, reject sections without the type
* Only parse the flag specific arguments if we have M or G
* Parse the corresponding arguments for M and G
We ignore the G arguments and flag for now.
llvm-svn: 117608
2010-10-28 21:33:33 +00:00
327a61423b
most simple arm instructions match correctly now,
...
it looks like we're not handling [] operands though
llvm-svn: 117607
2010-10-28 21:31:07 +00:00
1be0697ab9
fix the asmmatcher generator to handle targets with no RegisterPrefix
...
(like ARM) correctly. With this change, we can now match "bx lr"
because we recognize lr as a register.
llvm-svn: 117606
2010-10-28 21:28:42 +00:00
63760ba38e
Add support for the .string directive.
...
llvm-svn: 117592
2010-10-28 20:02:27 +00:00
3c5a54e4b9
Defined weak symbols should have non-zero value.
...
llvm-svn: 117585
2010-10-28 19:39:57 +00:00
29f70afbae
Fix relocations with renamed symbols.
...
llvm-svn: 117575
2010-10-28 19:08:03 +00:00
6cd76e63f8
Aliases defined with .symver should copy the binding of the symbols they alias.
...
Move the existing patching for undefined symbols so that all the patching
is done in the same function.
llvm-svn: 117570
2010-10-28 18:33:03 +00:00
f63da12be9
Teach the DAG combiner to fold a splat of a splat. Radar 8597790.
...
Also do some minor refactoring to reduce indentation.
llvm-svn: 117558
2010-10-28 17:06:14 +00:00
fdac6365ab
Implement .equ directive as a synonym to .set.
...
llvm-svn: 117553
2010-10-28 16:22:58 +00:00
efb139130f
Testcase for PR8494 (invalid bitcode crashing the bitcode reader).
...
llvm-svn: 117552
2010-10-28 15:57:30 +00:00
936ba3af28
Implement R_X86_64_DTPOFF32.
...
llvm-svn: 117548
2010-10-28 15:11:03 +00:00
2dbec3f762
Implement TLSLD.
...
llvm-svn: 117547
2010-10-28 15:02:40 +00:00
e8f08be11c
Implement DTPOFF.
...
llvm-svn: 117546
2010-10-28 14:48:59 +00:00
6f23eb380d
Implement TLSLDM.
...
llvm-svn: 117544
2010-10-28 14:37:09 +00:00
b3b49bbc39
Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind.
...
llvm-svn: 117543
2010-10-28 14:22:44 +00:00
ff310737e5
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
...
llvm-svn: 117531
2010-10-28 06:47:08 +00:00
0165e25564
Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful.
...
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.
llvm-svn: 117530
2010-10-28 06:46:17 +00:00
959807fa37
test/Transforms/SimplifyLibCalls/floor.ll: Mark as XFAIL:win32 due to lack of nearbyintf on MSVC. [PR8466]
...
llvm-svn: 117529
2010-10-28 06:46:04 +00:00
e2c211c1b9
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
...
llvm-svn: 117520
2010-10-28 02:00:25 +00:00
ff1c862f8e
- Assign load / store with shifter op address modes the right itinerary classes.
...
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
2010-10-28 01:49:06 +00:00
9c3f6bf2bf
Fix pastos in handling of AVX cvttsd2si, PR8491.
...
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
llvm-svn: 117514
2010-10-28 00:35:54 +00:00
2ef668840a
Add correct NEON encodings for vtbl and vtbx.
...
llvm-svn: 117513
2010-10-28 00:18:46 +00:00
14be930317
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
...
llvm-svn: 117512
2010-10-27 23:56:39 +00:00
16bb87a90e
Teach InstCombine not to use Add and Neg on FP. PR 8490.
...
llvm-svn: 117510
2010-10-27 23:45:18 +00:00
59bbc545e0
Shifter ops are not always free. Do not fold them (especially to form
...
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
llvm-svn: 117509
2010-10-27 23:41:30 +00:00
9f371e7efa
Tests for NEON encoding of vrev.
...
llvm-svn: 117502
2010-10-27 22:54:49 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
...
for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
ed9652f959
Provide correct encodings for the get_lane and set_lane variants of vmov.
...
llvm-svn: 117495
2010-10-27 21:28:09 +00:00
f8537165bd
Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE.
...
llvm-svn: 117494
2010-10-27 21:23:52 +00:00
5e7cb5fc27
Added the x86 instruction ud2b (2nd official undefined instruction).
...
llvm-svn: 117485
2010-10-27 20:46:49 +00:00
c7334a146e
SelectionDAG shuffle nodes do not allow operands with different numbers of
...
elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
llvm-svn: 117482
2010-10-27 20:38:28 +00:00
24c8b04d5f
Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32.
...
llvm-svn: 117481
2010-10-27 20:28:07 +00:00
40d24a4abf
Provide correct NEON encodings for vdup.
...
llvm-svn: 117475
2010-10-27 19:25:54 +00:00
095fa9e5cc
Set default type and flags for .init and .fini.
...
llvm-svn: 117471
2010-10-27 18:45:20 +00:00
fbdeab911a
Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun.
...
llvm-svn: 117469
2010-10-27 18:17:12 +00:00
5fa98baef7
Tests for NEON encoding of vcls, vclz, and vcnt.
...
llvm-svn: 117466
2010-10-27 18:05:25 +00:00
6b5af599c0
Tests for NEON encoding of vneg and vqneg.
...
llvm-svn: 117463
2010-10-27 17:57:26 +00:00
26496e6835
Produce an error for an invalid use of .symver.
...
llvm-svn: 117462
2010-10-27 17:56:18 +00:00
1e5eb98ed8
Tests for NEON encoding of vabs and vqabs.
...
llvm-svn: 117460
2010-10-27 17:50:07 +00:00
8576a42cf3
Add correct NEON encodings for vsli and vsri.
...
llvm-svn: 117459
2010-10-27 17:40:08 +00:00
d7e8135e1e
Add correct NEON encodings for vsra and vrsra.
...
llvm-svn: 117458
2010-10-27 17:29:29 +00:00
cc1b168ef6
Symbols defined as the difference of other two end up in the ABS section.
...
llvm-svn: 117451
2010-10-27 16:04:30 +00:00
eb0c2c170d
Add support for the .symver directive. This is really ugly, but most of it is
...
contained in the ELF object writer.
llvm-svn: 117448
2010-10-27 15:18:17 +00:00
9ad2166899
Yet another tweak to X86 instructions to add ud2a as an alias to ud2
...
(still to add ud2b).
llvm-svn: 117435
2010-10-27 03:01:02 +00:00
20b021c970
Another tweak to X86 instructions to add the missing flex instruction (without
...
the wait prefix).
llvm-svn: 117434
2010-10-27 02:53:04 +00:00
a1917c7555
Tweaks to X86 instructions to allow the 'w' suffix in places it makes
...
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler
allows for these instructions. Done differently than in r117031 that
caused a valgrind error which was later reverted.
llvm-svn: 117433
2010-10-27 02:32:19 +00:00
ba985d9dd5
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
...
will accept versions that the darwin assembler allows. Forms ending in "pi" and
forms without all the operands.
llvm-svn: 117427
2010-10-27 00:59:28 +00:00
825b2d1946
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
...
llvm-svn: 117411
2010-10-26 22:50:46 +00:00
2888e2c7f9
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
...
llvm-svn: 117402
2010-10-26 21:58:41 +00:00
3fe94f1e9f
FileCheck'ize
...
llvm-svn: 117401
2010-10-26 21:26:47 +00:00
c4126a1a2c
Add tests for NEON encoding of vshll.
...
llvm-svn: 117399
2010-10-26 21:21:47 +00:00
0fbb20769f
Tests for NEON encoding of vshr.
...
llvm-svn: 117396
2010-10-26 21:08:42 +00:00
3665fee8de
Provide correct NEON encodings for vshl, register and immediate forms.
...
llvm-svn: 117394
2010-10-26 20:56:57 +00:00
c9fb35e73b
Add support for .ident.
...
llvm-svn: 117389
2010-10-26 19:35:47 +00:00
db192ba90f
Tests for NEON encoding of vrecpe, vrecps, vrsqrte, and vsqrts.
...
llvm-svn: 117385
2010-10-26 18:43:13 +00:00
b3bcf529fc
Tests for NEON encodings of vpmin and vpmax.
...
llvm-svn: 117382
2010-10-26 18:31:47 +00:00
691ce68d3c
Add correct NEON encoding for vpadal.
...
llvm-svn: 117380
2010-10-26 18:18:03 +00:00
035b3261ee
Tests for NEON encoding of vpadd and vpaddl.
...
llvm-svn: 117377
2010-10-26 18:04:51 +00:00
284cb361d1
Add NEON encodings for vmov and vmvn of immediates.
...
llvm-svn: 117374
2010-10-26 17:40:54 +00:00
e8ae98817a
Implement some relaxations for arithmetic instructions. The limitation
...
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.
llvm-svn: 117364
2010-10-26 14:09:12 +00:00
a49d062234
Change v64 datalayout in SPU.
...
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays,
we use array alignment for v64 too. This makes the
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.
This also makes an "unaligned store" test to be
aligned, with different (but functionally equivalent)
code generated.
llvm-svn: 117360
2010-10-26 10:45:47 +00:00
e1961fe289
When the "true" and "false" blocks of a diamond if-conversion are the same,
...
do not double-count the duplicate instructions by counting once from the
beginning and again from the end. Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end. Radar 8589805.
This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction. That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.
llvm-svn: 117333
2010-10-26 00:02:24 +00:00
c0f777afbf
Tests for NEON encoding of vmax.
...
llvm-svn: 117327
2010-10-25 23:45:34 +00:00
144c3f8c6a
Tests for NEON encoding of vmin.
...
llvm-svn: 117326
2010-10-25 23:35:36 +00:00
ec57ac1c3c
An stdcall function calling a non-stdcall function
...
cannot use tailcall. PR 8461.
llvm-svn: 117322
2010-10-25 22:17:05 +00:00
1f6aad053d
Add correct encodings for NEON vabal.
...
llvm-svn: 117315
2010-10-25 21:29:04 +00:00
b9c91679aa
Add correct NEON encodings for vaba.
...
llvm-svn: 117309
2010-10-25 20:52:57 +00:00
12214ddaa3
Tests for NEON encoding of vabdl.
...
llvm-svn: 117303
2010-10-25 20:36:28 +00:00
64aa05f865
Add tests for NEON encoding of vabd.
...
llvm-svn: 117302
2010-10-25 20:29:27 +00:00
b3a48f3459
MC/AsmParser: Fix relative precedence of {+,-} and comparison ops.
...
llvm-svn: 117299
2010-10-25 20:18:56 +00:00
7484d2cbec
MC/AsmLexer: Fix bug in source location for Slash token.
...
llvm-svn: 117298
2010-10-25 20:18:53 +00:00
95db1cc022
tweak test.
...
llvm-svn: 117297
2010-10-25 20:18:49 +00:00
0c193ca626
MC/AsmParser: Rewrite test to actually check some parts of expression parsing,
...
now that we have macros and friends. Uncovered a bug in macro expansion...
llvm-svn: 117295
2010-10-25 20:18:41 +00:00
dd001b89d7
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
...
llvm-svn: 117294
2010-10-25 20:17:22 +00:00
dea09c7564
Provide correct NEON encodings for vbsl.
...
llvm-svn: 117293
2010-10-25 20:13:13 +00:00
2477446ee5
Add correct instruction encodings for vbic, vorn, and vmvn.
...
llvm-svn: 117282
2010-10-25 18:43:52 +00:00
dff239c5f9
Provide correct NEON encodings for vand, veor, and vorr.
...
llvm-svn: 117279
2010-10-25 18:28:30 +00:00
d9cdda9ddc
Add tests for NEON encoding of vtst.
...
llvm-svn: 117277
2010-10-25 18:10:34 +00:00
feb3ee0c93
Add NEON encoding tests for vcgt and vacgt.
...
llvm-svn: 117276
2010-10-25 18:03:59 +00:00
0ed1543d4e
Add support for emitting ARM file attributes.
...
llvm-svn: 117275
2010-10-25 17:50:35 +00:00
e5d0677173
Add tests for NEON encodings of vcge and vacge.
...
llvm-svn: 117274
2010-10-25 17:49:32 +00:00
c178b80f65
Add a warning about our inability to test the encoding of vceq with immediate zero.
...
llvm-svn: 117273
2010-10-25 17:33:02 +00:00
02917f5b1b
Add tests for NEON encoding of vceq.
...
llvm-svn: 117270
2010-10-25 17:20:26 +00:00
a9ad6c0645
Add tests for NEON encoding of vsubhn and vrsubhn.
...
llvm-svn: 117269
2010-10-25 17:12:46 +00:00
2e20dfb0f2
Fix a case where instcombine was stripping metadata (and alignment)
...
from stores when folding in bitcasts.
llvm-svn: 117265
2010-10-25 16:16:27 +00:00
31c803b2ba
Fix PR8445: a block with no predecessors may be the entry block, in which case
...
it isn't unreachable and should not be zapped. The check for the entry block
was missing in one case: a block containing a unwind instruction. While there,
do some small cleanups: "M" is not a great name for a Function* (it would be
more appropriate for a Module*), change it to "Fn"; use Fn in more places.
llvm-svn: 117224
2010-10-24 12:23:30 +00:00
358900d569
Add tests for NEON encoding of vqsub.
...
llvm-svn: 117214
2010-10-23 18:02:16 +00:00
aa19ee17c0
X86: Emit _fltused instead of __fltused on Windows x64.
...
llvm-svn: 117205
2010-10-23 09:06:59 +00:00
f4a6809231
Remove -llvmc-temp-hack from tblgen.
...
llvm-svn: 117197
2010-10-23 07:32:53 +00:00
92644efaf8
Add tests for NEON encoding of vhsub.
...
llvm-svn: 117189
2010-10-22 23:58:22 +00:00
0ce06c08fb
Add a CMP test.
...
llvm-svn: 117187
2010-10-22 23:48:01 +00:00
f4e1a09d38
Add tests for NEON encoding of vsubw.
...
llvm-svn: 117186
2010-10-22 23:46:07 +00:00
4663dc72e2
tidy up
...
llvm-svn: 117185
2010-10-22 23:46:04 +00:00
9ef5c507ce
Add tests for NEON encoding of vsubl.
...
llvm-svn: 117183
2010-10-22 23:36:36 +00:00
c372775cc8
Add tests for NEON encoding of vsub.
...
llvm-svn: 117177
2010-10-22 23:21:04 +00:00
cb5c1b75fe
Add tests for NEON encoding of vqdmlsl.
...
llvm-svn: 117173
2010-10-22 23:08:47 +00:00
d655a80774
Add tests for NEON encoding of vmlsl.
...
llvm-svn: 117171
2010-10-22 23:02:27 +00:00
b40a60fa2f
tidy up.
...
llvm-svn: 117166
2010-10-22 22:15:48 +00:00
2c9ae05c67
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
...
llvm-svn: 117165
2010-10-22 22:12:16 +00:00
3565b0a2e2
Remove duplicate test.
...
llvm-svn: 117158
2010-10-22 22:04:28 +00:00
6d993fa1a6
tidy up.
...
llvm-svn: 117157
2010-10-22 22:01:56 +00:00
db7415075d
FileCheck-ize a few tests.
...
llvm-svn: 117156
2010-10-22 21:55:03 +00:00
a4e231c880
Teach instcombine to set the alignment arguments for NEON load/store intrinsics.
...
llvm-svn: 117154
2010-10-22 21:41:48 +00:00
3c4f72c9f8
Add tests for the correct encoding of NEON vmls.
...
llvm-svn: 117145
2010-10-22 20:31:24 +00:00
9d0122af7d
Add correct NEON encodings for vqdmlal.
...
llvm-svn: 117134
2010-10-22 19:35:48 +00:00
2b80543fc2
Add the encoding information for the rest of the ARM mode multiply instructions.
...
llvm-svn: 117133
2010-10-22 19:15:30 +00:00
3d0264667f
Provide correct encodings for NEON vmlal.
...
llvm-svn: 117131
2010-10-22 19:05:25 +00:00
f48719f1b5
Provide correct NEON encodings for vmla.
...
llvm-svn: 117126
2010-10-22 18:54:37 +00:00
a8c4143bf6
Temporarily revert r117079; it broke a tester. Radar 6635085.
...
llvm-svn: 117122
2010-10-22 18:44:22 +00:00
6956a60563
More ARM multiply instuction binary encodings.
...
llvm-svn: 117121
2010-10-22 18:35:16 +00:00
f6659997a1
Add testscases for encoding of NEON vdqmull.
...
llvm-svn: 117115
2010-10-22 17:57:37 +00:00
22261600a8
More ARM multiply instruction encoding information.
...
llvm-svn: 117108
2010-10-22 17:16:17 +00:00
c7e0dcf13f
test/Makefile: Force lit -j1 on Cygwin.
...
lit -jN causes crash on Cygwin's python.
llvm-svn: 117093
2010-10-22 09:40:37 +00:00
edd006c1c3
Reverting r117031 to cleanup valgrind errors.
...
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.
llvm-svn: 117087
2010-10-22 03:58:29 +00:00
9f6c622f88
Fixed handling of immediate operand sizes, which
...
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix. Also added
a test case for this.
llvm-svn: 117084
2010-10-22 01:24:11 +00:00
cdc55bc680
Test case for r117075. Radar 6635085.
...
llvm-svn: 117079
2010-10-21 22:43:32 +00:00
28418de7ee
Add tests for NEON encoding of vmull.
...
llvm-svn: 117077
2010-10-21 22:19:53 +00:00
a97becfaac
ARM binary encodings for MVN variants.
...
llvm-svn: 117076
2010-10-21 22:19:32 +00:00
22c940c9ab
Add tests for NEON encoding of vqdmulh and vqrdmulh.
...
llvm-svn: 117074
2010-10-21 22:05:33 +00:00
5edb03ee57
ARM Binary encoding information for BFC/BFI instructions.
...
llvm-svn: 117072
2010-10-21 22:03:21 +00:00
eff79f13a6
Add tests for NEON vmul encoding.
...
llvm-svn: 117069
2010-10-21 21:51:58 +00:00
6e1cf114f9
Rename this test to better reflect its contents.
...
llvm-svn: 117067
2010-10-21 21:40:15 +00:00
c47913acd2
Add tests for NEON encodings of vaddhn and vraddhn.
...
llvm-svn: 117064
2010-10-21 20:56:57 +00:00
d8be664273
Add tests for NEON encodings of vqadd, which was already correctly encoded.
...
llvm-svn: 117059
2010-10-21 20:42:04 +00:00
6b7e401049
Add correct NEON encodings for vhadd and vrhadd.
...
llvm-svn: 117047
2010-10-21 18:55:04 +00:00
9561084188
Add correct encodings for NEON vaddw.s* and vaddw.u*.
...
llvm-svn: 117040
2010-10-21 18:20:25 +00:00
15c97706e8
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
...
llvm-svn: 117039
2010-10-21 18:09:17 +00:00
8ba86f801d
Do not recurse into symbol refs that have a variant kind. This prevents us
...
from losing the variant when producing a relocation on an alias.
llvm-svn: 117037
2010-10-21 18:00:20 +00:00
0138a05557
More tweaks to X86 instructions to allow the 'w' suffix in places it makes
...
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler allows
for these instructions. Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).
llvm-svn: 117031
2010-10-21 17:16:46 +00:00
2a7d269a2b
Fix whitespace.
...
llvm-svn: 117002
2010-10-21 06:25:08 +00:00
c16f77fb27
Recommit 116986 with capitalization typo fixed.
...
llvm-svn: 116993
2010-10-21 03:57:26 +00:00
f4ebec03e0
putback r116983 and fix simple-fp-encoding.ll tests
...
llvm-svn: 116992
2010-10-21 03:40:16 +00:00
078db00f1d
Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it
...
compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.
llvm-svn: 116991
2010-10-21 03:34:22 +00:00
9e00f27e14
Revert r116983, which is breaking all the buildbots.
...
llvm-svn: 116987
2010-10-21 03:11:16 +00:00
f608ac4db9
Major update of the MicroBlaze backend. The new features are:
...
1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
llvm-svn: 116986
2010-10-21 03:09:55 +00:00
15c2ac90ec
Add missing scheduling itineraries for transfers between core registers and VFP registers.
...
llvm-svn: 116983
2010-10-21 01:12:00 +00:00
6083502848
Implement correct encodings for NEON vadd, both integer and floating point.
...
llvm-svn: 116981
2010-10-21 00:48:00 +00:00
a65f914bb0
Add encoding for moving a value between two ARM core registers and a doublework
...
extension register.
llvm-svn: 116970
2010-10-20 23:37:40 +00:00
058190507b
Add encodings for movement between ARM core registers and single-precision
...
registers.
llvm-svn: 116961
2010-10-20 22:44:54 +00:00
55a028680c
Add some comments.
...
llvm-svn: 116957
2010-10-20 22:04:02 +00:00
87066f0677
More accurate estimate / tracking of register pressure.
...
- Initial register pressure in the loop should be all the live defs into the
loop. Not just those from loop preheader which is often empty.
- When an instruction is hoisted, update register pressure from loop preheader
to the original BB.
- Treat only use of a virtual register as kill since the code is still SSA.
llvm-svn: 116956
2010-10-20 22:03:58 +00:00
ff37675c72
Fix crash introduced in 116852. 8573915.
...
llvm-svn: 116955
2010-10-20 22:03:37 +00:00
ef3ba55e52
Cut unneeded global variable.
...
llvm-svn: 116953
2010-10-20 22:01:39 +00:00
89f6613e76
Handle _GLOBAL_OFFSET_TABLE_ correctly.
...
llvm-svn: 116932
2010-10-20 16:46:08 +00:00
710a2d9d46
Enable using vdup for vector constants which are splat of
...
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
llvm-svn: 116852
2010-10-19 20:00:17 +00:00
63c7608c34
Re-enable register pressure aware machine licm with fixes. Hoist() may have
...
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
llvm-svn: 116845
2010-10-19 18:58:51 +00:00
e8b3711ae9
Fixing r116753 r116756 r116777
...
The failures in r116753 r116756 were caused by a python issue -
Python likes to append 'L' suffix to stringified numbers if the number
is larger than a machine int. Unfortunately, this causes a divergence of
behavior between 32 and 64 bit python versions.
I re-crafted elf-dump/common_dump to take care of these issues by:
1. always printing 0x (makes for easy sed/regex)
2. always print fixed length (exactly 2 + numBits/4 digits long)
by mod ((2^numBits) - 1)
3. left-padded with '0'
There is a residual common routine that is also used by
macho-dump (dataToHex) , so I left the 'section_data' test values alone.
llvm-svn: 116823
2010-10-19 17:39:10 +00:00
418204e523
Revert r116781 "- Add a hook for target to determine whether an instruction def
...
is", which breaks some nightly tests.
llvm-svn: 116816
2010-10-19 17:14:24 +00:00
2072db24ed
GlobalOpt: EvaluateFunction() must not evaluate stores to weak_odr globals.
...
Fixes PR8389.
llvm-svn: 116812
2010-10-19 16:47:23 +00:00
18d3e435cb
Add test case mov.ll for PTX device function
...
llvm-svn: 116806
2010-10-19 13:21:51 +00:00
e73bc89093
Fix PR8300 by remembering to keep the bitcast in all cases.
...
llvm-svn: 116788
2010-10-19 02:02:57 +00:00
8249dfe6ce
- Add a hook for target to determine whether an instruction def is
...
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
llvm-svn: 116781
2010-10-19 00:55:07 +00:00
eac5e381cc
Speculatively revert 116753 and 116756 to attempt to fix the bots.
...
llvm-svn: 116777
2010-10-19 00:19:49 +00:00
b6d61dc291
Support alignment for NEON vld-lane and vst-lane instructions.
...
llvm-svn: 116776
2010-10-19 00:16:32 +00:00
49843c0162
Added a few tweaks to the Intel Descriptor-table support instructions to allow
...
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes. This is again for use just with assembly source for llvm-mc .
llvm-svn: 116773
2010-10-19 00:01:44 +00:00
7b92c2a9a0
Revert r116220 - thus turning arm fast isel back on by default.
...
llvm-svn: 116762
2010-10-18 22:53:53 +00:00
d4cc3d420a
Get rid of unneeded FormatOutput global variable
...
llvm-svn: 116756
2010-10-18 21:59:38 +00:00
eae048885d
Changed elf-dump to output hex format by default.
...
Also updated tests.
llvm-svn: 116753
2010-10-18 21:32:41 +00:00
408beac597
Don't pass the raw invalid pointer used to represent conflicting
...
TBAA information to AliasAnalysis.
llvm-svn: 116751
2010-10-18 21:28:00 +00:00
fe8abf88a0
Add a basic testcase for TBAA-aware LICM.
...
llvm-svn: 116745
2010-10-18 21:00:09 +00:00
fba9f74932
Implement R_386_GOT32.
...
llvm-svn: 116744
2010-10-18 20:47:21 +00:00
0a5314fdb3
Relocate with .bss instead of using the symbol. Matches gas behavior.
...
llvm-svn: 116741
2010-10-18 20:25:33 +00:00
f7a5e20372
Run tbaa before basicaa, since that's how it's expected to be used.
...
llvm-svn: 116731
2010-10-18 18:45:59 +00:00
e3dc9e2ea1
Produce ELF::R_386_GOTPC relocations.
...
llvm-svn: 116728
2010-10-18 18:36:12 +00:00
33fcde9b9c
Make TypeBasedAliasAnalysis default to doing nothing, with a command-line
...
option to enable it.
llvm-svn: 116722
2010-10-18 18:17:47 +00:00
02538ac4d3
Make BasicAliasAnalysis a normal AliasAnalysis implementation which
...
does normal initialization and normal chaining. Change the default
AliasAnalysis implementation to NoAlias.
Update StandardCompileOpts.h and friends to explicitly request
BasicAliasAnalysis.
Update tests to explicitly request -basicaa.
llvm-svn: 116720
2010-10-18 18:04:47 +00:00
b9783dd9bc
Added a handful of x86-32 instructions that were missing so that llvm-mc would
...
be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
llvm-svn: 116716
2010-10-18 17:04:36 +00:00
3521f8467d
Produce a R_386_PLT32 when needed. Moved the default cases of switches to the
...
start for consistency.
llvm-svn: 116715
2010-10-18 16:58:03 +00:00
4464e0858f
Handle GOTOFF correctly on i386.
...
llvm-svn: 116711
2010-10-18 16:38:04 +00:00
5f2034c455
Improve lowering of sext to i128 on SPU.
...
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.
llvm-svn: 116701
2010-10-18 09:34:19 +00:00
4262a22225
Add a MCObjectFormat class so that code common to all targets that use a
...
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
llvm-svn: 116675
2010-10-16 18:23:53 +00:00
0d14b5b0fa
Unbreak test on non-COFF targets.
...
llvm-svn: 116669
2010-10-16 11:27:13 +00:00
17990d5690
MC-COFF: Add support for default-null weak externals.
...
llvm-svn: 116666
2010-10-16 08:25:57 +00:00
5e683250ee
X86-Windows: Emit an undefined global __fltused symbol when targeting Windows
...
if any floating point arguments are passed to an external function.
llvm-svn: 116665
2010-10-16 08:25:41 +00:00
18e4fed3fa
Generalize MemCpyOpt's handling of call slot forwarding to function properly when the call slot
...
forwarding is implemented with a load/store pair rather than a memcpy.
llvm-svn: 116637
2010-10-15 22:52:12 +00:00
3ba051a4f6
llvmc: Add a test for the -c flag.
...
llvm-svn: 116611
2010-10-15 19:30:49 +00:00
68a335e185
ARM mode encoding information for UBFX and SBFX instructions.
...
llvm-svn: 116588
2010-10-15 17:15:16 +00:00
f28cc03802
FileCheckize
...
llvm-svn: 116581
2010-10-15 16:06:42 +00:00
fbcf0db7ee
Refactor code a bit and avoid creating unnecessary entries in the string
...
map.
llvm-svn: 116579
2010-10-15 15:39:06 +00:00
59351844e1
ARM instructions that are both predicated and set the condition codes
...
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
0b5c743811
Simplify test file a bit.
...
llvm-svn: 116540
2010-10-14 23:32:44 +00:00
89efff3763
Add testcase for RRX and ASRS (which effectively tests MOVs, since those
...
are just forms of that instruction).
llvm-svn: 116538
2010-10-14 23:29:18 +00:00
8b6a9c1574
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
...
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
llvm-svn: 116534
2010-10-14 22:57:13 +00:00
062749cb25
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
...
pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
eafcb27ded
MOVi16 and MOVT ARM mode encodings.
...
llvm-svn: 116498
2010-10-14 18:54:27 +00:00
bee6e9f8e0
Remove some code duplication.
...
llvm-svn: 116484
2010-10-14 16:34:44 +00:00
793d141b7d
Comments.
...
llvm-svn: 116476
2010-10-14 13:43:20 +00:00
6f52f8a87d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
...
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
0441c6cba0
Add encoding for 'fmstat'.
...
llvm-svn: 116466
2010-10-14 01:19:34 +00:00
0825f3e441
- Add encodings for multiply add/subtract instructions in all their glory.
...
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
llvm-svn: 116464
2010-10-14 01:02:08 +00:00
b9681ad442
fix a bug I introduced, no idea how this didn't repro right.
...
llvm-svn: 116462
2010-10-14 00:30:00 +00:00
c7bd5740eb
hack to unbreak buildbots
...
llvm-svn: 116461
2010-10-14 00:26:10 +00:00
698661c741
add uadd_ov/usub_ov to apint, consolidate constant folding
...
logic to use the new APInt methods. Among other things this
implements rdar://8501501 - llvm.smul.with.overflow.i32 should constant fold
which comes from "clang -ftrapv", originally brought to my attention from PR8221.
llvm-svn: 116457
2010-10-14 00:05:07 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
f106ecfa59
Add MC encodings for VCVT* instrunctions.
...
llvm-svn: 116431
2010-10-13 20:58:46 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
651dc7c9e9
Add ARM mode operand encoding information for ADDE/SUBE instructions.
...
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
2216af3fa8
Fix another case where we were preferring instructions with large
...
immediates instead of 8 bits ones.
llvm-svn: 116410
2010-10-13 17:14:25 +00:00
8ea9b0eb32
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
...
8 bit constants can be used.
llvm-svn: 116403
2010-10-13 13:31:20 +00:00
6e27b4f530
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
...
just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
576fd0b110
Add encodings for VCVT instructions.
...
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
8c519c0d4b
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
da4ddf0fcf
Add VCMPZ and VABS.
...
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
f9ca535495
Refactor VCMP instructions.
...
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
a237bdbe52
FileCheckize this in a hope to quiet a valgrind warning on grep.
...
llvm-svn: 116376
2010-10-12 23:47:58 +00:00
7dd8c0b991
Add encodings for VNMUL[SD].
...
llvm-svn: 116375
2010-10-12 23:47:37 +00:00
a06aee826c
Add encodings for VDIV and VMUL.
...
llvm-svn: 116370
2010-10-12 23:22:27 +00:00
d5f8c3350d
Be nitpicky and line up the comments.
...
llvm-svn: 116365
2010-10-12 23:14:03 +00:00
646a506724
Add encoding for VSUB and VCMP.
...
Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
9513a7e87f
Don't need to specify calling convention. Add 'readnone' to functions.
...
llvm-svn: 116354
2010-10-12 22:24:10 +00:00
ac6cd00706
Encoding for VADDD. Plus a test for the VFP instructions.
...
llvm-svn: 116348
2010-10-12 22:08:41 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
...
ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
65eb03ed6b
Add a simple testcase for tbaa.
...
llvm-svn: 116272
2010-10-11 23:54:13 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
...
register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
3e02306fed
PR8297
...
llvm-svn: 116223
2010-10-11 21:08:42 +00:00
6c4353ecee
PowerPC varargs functions store live-in registers on the stack. Make sure we use
...
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.
This fixes PR8357.
llvm-svn: 116222
2010-10-11 20:43:09 +00:00
e2a0b6841a
Found a bug turning this on by default. Disable again for now.
...
llvm-svn: 116220
2010-10-11 20:26:21 +00:00
6002b3b3e1
Remove now non-existent option.
...
llvm-svn: 116219
2010-10-11 20:21:21 +00:00
e01c9001c9
Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
...
llvm-svn: 116214
2010-10-11 19:02:04 +00:00
1ef5e84c31
Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if
...
it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.
llvm-svn: 116190
2010-10-11 05:44:40 +00:00
00765e5be0
X86: MinGW should always use libgcc on Windows.
...
llvm-svn: 116177
2010-10-10 23:11:06 +00:00
7a573a5e1f
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
...
llvm-svn: 116174
2010-10-10 22:04:34 +00:00
f8f7537a77
force a triple, varargs isn't supported with the SVR4 ABI the buildbot tells me.
...
llvm-svn: 116170
2010-10-10 18:59:01 +00:00
d10babfd65
fix the expansion of va_arg instruction on PPC to know the arg
...
alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
llvm-svn: 116168
2010-10-10 18:34:00 +00:00
b8d7efe785
Now using a variant of the existing inlining heuristics to decide whether to create a given specialization of a function in PartialSpecialization. If the total performance bonus across all callsites passing the same constant exceeds the specialization cost, we create the specialization.
...
llvm-svn: 116158
2010-10-09 22:06:36 +00:00
a6a984bd96
MC-COFF: Fix .bss section size. Fixes PR8335. Patch by NAKAMUTA Takumi!
...
llvm-svn: 116155
2010-10-09 16:04:45 +00:00
b20b08f898
Don't test a removed function.
...
llvm-svn: 116154
2010-10-09 15:53:25 +00:00
86bbd71088
MC-COFF: Implement InitSections. Fixes PR8335.
...
llvm-svn: 116151
2010-10-09 15:44:27 +00:00
c8dbdfd4ba
MC-COFF: Add COFFAsmParser. Completes PR8343.
...
llvm-svn: 116150
2010-10-09 11:01:07 +00:00
05f13e94bf
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
748265b0da
Simplify test and move into a generic "crash" ll file.
...
llvm-svn: 116130
2010-10-09 00:29:04 +00:00
59ebe44049
Check to make sure that the iterator isn't at the beginning of the basic block
...
before decrementing. <rdar://problem/8529919>
llvm-svn: 116126
2010-10-09 00:03:48 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
af8b4871a8
Call InitSections in llc and clang so that the binaries produced by them
...
are easier to diff with those produced by llvm-mc.
llvm-svn: 116095
2010-10-08 19:37:38 +00:00
d57f9ecd4a
Recommit 116056, now with the missing file...
...
llvm-svn: 116083
2010-10-08 19:24:18 +00:00
cf97db2402
reverting 116056: win64_params.ll may need to be conditionalized?
...
llvm-svn: 116063
2010-10-08 17:22:42 +00:00
a07b5c291d
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
...
llvm-svn: 116056
2010-10-08 10:31:30 +00:00
056b694de1
Change register allocation order for ARM VFP and NEON registers to put the
...
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
llvm-svn: 116055
2010-10-08 06:15:13 +00:00
3e210eb398
testcase that goes with r116053
...
llvm-svn: 116054
2010-10-08 05:12:30 +00:00
8ed76f87cf
rename test
...
llvm-svn: 116052
2010-10-08 05:05:06 +00:00
420cf26d99
merge tests
...
llvm-svn: 116051
2010-10-08 05:04:58 +00:00
6a8a65cb43
filecheckize.
...
llvm-svn: 116050
2010-10-08 05:02:29 +00:00
dd77477690
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
...
reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
llvm-svn: 116040
2010-10-08 03:57:25 +00:00
00ee155b25
Fix Formatting.
...
llvm-svn: 116038
2010-10-08 03:17:21 +00:00
8eb636e5de
MC-COFF: Fix Simple and Complex type. Fixes PR8320.
...
llvm-svn: 116037
2010-10-08 03:17:11 +00:00
efdf08b5b8
Revert "reimplement the second half of the or/add optimization. We should now",
...
which depends on r116007, which I am about to revert.
llvm-svn: 116031
2010-10-08 02:07:26 +00:00
134f415bf8
reimplement the second half of the or/add optimization. We should now
...
only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
llvm-svn: 116026
2010-10-08 01:05:10 +00:00
42a07e8545
Add test file for simple ARM binary encodings with MC
...
llvm-svn: 116024
2010-10-08 00:47:59 +00:00
00be34d009
MC-COFF: Add test for my last commit.
...
llvm-svn: 116015
2010-10-08 00:00:28 +00:00
57da4caa85
Remove LoopIndexSplit pass. It is neither maintained nor used by anyone.
...
llvm-svn: 116004
2010-10-07 23:29:37 +00:00
ae8d67d3bb
convert cmp to use a multipattern
...
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
5c31bf0619
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
...
llvm-svn: 115977
2010-10-07 20:50:20 +00:00
1666b61357
MC-COFF: Fix symbol aliases. Fixes PR8251.
...
llvm-svn: 115909
2010-10-07 06:29:33 +00:00
efc22274cd
test: Fix binary stdin issues with coff-dump on Windows.
...
llvm-svn: 115908
2010-10-07 06:29:21 +00:00
742adc328a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
5f2d6a5cd9
Get binding and visibility info from the the alias, but Type from the symbol
...
being aliased.
llvm-svn: 115836
2010-10-06 21:02:29 +00:00
d444577382
If a symbol is global, reloc against it even if it is in a mergeable section.
...
llvm-svn: 115817
2010-10-06 19:27:21 +00:00
83b2a3337f
Make sure weak symbols are listed after the local ones.
...
llvm-svn: 115795
2010-10-06 16:47:31 +00:00
8f3d2c9058
Correctly handle GOTPCREL relocations.
...
llvm-svn: 115793
2010-10-06 16:23:36 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
28f034c21a
Generalize tblgen's dag parsing logic to handle arbitrary expressions
...
as the operator of the dag. Specifically, this allows parsing things
like (F.x 4) in addition to just (a 4).
Unfortunately, this runs afoul of an idiom being used by llvmc. It
is using dags like (foo [1,2,3]) to represent a list of stuff being
passed into foo. With this change, this is parsed as a [1,2,3]
subscript on foo instead of being the first argument to the dag.
Cope with this in the short term by requiring a "-llvmc-temp-hack"
argument to tblgen to get the old parsing behavior.
llvm-svn: 115742
2010-10-06 04:55:48 +00:00
805b74d650
rename add some comments.
...
llvm-svn: 115741
2010-10-06 04:37:17 +00:00
7d5bb96723
filecheckize
...
llvm-svn: 115740
2010-10-06 04:36:30 +00:00
9402633637
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
d7565c3a06
Use a relocation against the symbol if it is a PLT and the symbol is in another
...
section. Common because of linkonce sections.
llvm-svn: 115718
2010-10-05 23:57:26 +00:00
7538ed80a9
enhance tblgen to support anonymous defm's, use this to
...
simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
0ad137e98e
Implement more alias cases.
...
llvm-svn: 115699
2010-10-05 22:26:43 +00:00
10a0fdeab5
PSHUFW is in SSE, not SSSE3.
...
llvm-svn: 115691
2010-10-05 21:58:12 +00:00
13111b08fb
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
...
gross hack (having the asmmatcher handle the alias).
llvm-svn: 115685
2010-10-05 21:09:45 +00:00
c58a37ea51
Don't crash in a strange .size directive.
...
llvm-svn: 115684
2010-10-05 21:02:45 +00:00
a3b34ed2df
MC-COFF: Fix (PR8278) temporary symbol relocations.
...
llvm-svn: 115656
2010-10-05 19:48:03 +00:00
b91bac6c96
Add support for a fill value in the .zero directive.
...
llvm-svn: 115655
2010-10-05 19:42:57 +00:00
b1d0789357
Implement a simple alias case and refactor the code a bit so that the
...
isInSymtab and isLocal logic in the two loops don't get easily out of sync.
llvm-svn: 115643
2010-10-05 18:01:23 +00:00
8ccdd25fbd
test/COFF: Fix symbol indexes and names. Update tests to match.
...
llvm-svn: 115642
2010-10-05 17:57:08 +00:00
f6230d1d4b
test/COFF: Remove temp file usage.
...
llvm-svn: 115641
2010-10-05 17:56:56 +00:00
e58f37f74d
test/coff-dump: Support reading from stdin.
...
llvm-svn: 115640
2010-10-05 17:56:46 +00:00
868aaf3c3d
Cleanup Whitespace.
...
llvm-svn: 115639
2010-10-05 17:56:37 +00:00
d8d1dcc09a
Use a more efficient lowering of uint64_t --> float that can take advantage of hardware signed integer conversion without
...
having to do a double cast (uint64_t --> double --> float). This is based on the algorithm from compiler_rt's __floatundisf
for X86-64.
llvm-svn: 115634
2010-10-05 17:24:05 +00:00
d03e81dba8
Produce a undefined reference to _GLOBAL_OFFSET_TABLE_ when needed.
...
llvm-svn: 115623
2010-10-05 15:48:37 +00:00
259bcdad06
Tests that now pass.
...
llvm-svn: 115622
2010-10-05 15:43:32 +00:00
7681b41720
test/CodeGen/X86/atomic_op.ll: Rename @main to @func. Extra sequences will be inserted to @main as prologue on cygming, to fail.
...
llvm-svn: 115611
2010-10-05 11:16:24 +00:00
6296bbbb65
Added a testcase for the ENTER instruction.
...
llvm-svn: 115580
2010-10-05 00:21:40 +00:00
402e54822b
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
...
it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
llvm-svn: 115552
2010-10-04 20:24:01 +00:00
fd1fff8b19
Implement ELF::R_X86_64_GOTPCREL.
...
llvm-svn: 115547
2010-10-04 19:51:39 +00:00
baadbd554a
Produce a R_X86_64_PLT32 when needed.
...
llvm-svn: 115541
2010-10-04 19:04:13 +00:00
b2c4ca6433
Produce a R_X86_64_GOT32 when needed.
...
llvm-svn: 115537
2010-10-04 18:44:25 +00:00
87f77b5f9a
Add hook in MCSection to decide when to use "optimized nops", for each
...
section kind. Previously, optimized nops were only used for MachO.
Also added tests for ELF and COFF.
llvm-svn: 115523
2010-10-04 17:32:41 +00:00
da0e3d07b2
Include the section address in the computation of the relocation.
...
llvm-svn: 115509
2010-10-04 15:59:01 +00:00
7c48b06930
Correctly compute the relocation when it is not in the first fragment.
...
llvm-svn: 115506
2010-10-04 15:28:43 +00:00
d77a443631
va_args support for Win64.
...
Patch by Cameron!
llvm-svn: 115480
2010-10-03 22:52:07 +00:00
ff85688559
Properly emit stack probe on win64 (for non-mingw targets).
...
Based on the patch by Cameron Esfahani!
llvm-svn: 115479
2010-10-03 22:02:38 +00:00
bb48e26732
Add 3DNowA instructions.
...
llvm-svn: 115477
2010-10-03 20:23:13 +00:00
f909b07340
unbreak buildbot
...
llvm-svn: 115476
2010-10-03 20:02:48 +00:00
d3593c3a8e
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
...
llvm-svn: 115473
2010-10-03 19:09:13 +00:00
b44b202d66
add support for the prefetch/prefetchw instructions, move femms into
...
the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
llvm-svn: 115468
2010-10-03 18:42:30 +00:00
3a0a620c2e
what the heck, add support for the rest of the 3dNow! binary operations.
...
llvm-svn: 115467
2010-10-03 18:24:18 +00:00
45270db916
Implement support for the bizarre 3DNow! encoding (which is unlike anything
...
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
llvm-svn: 115466
2010-10-03 18:08:05 +00:00
5d9089ae14
Add test to make sure that the MMX intrinsic calls make it out the other end in
...
tact.
llvm-svn: 115458
2010-10-03 03:30:30 +00:00
14d07adf0b
Auto-upgrade tests for the new MMX intrinsic calls.
...
llvm-svn: 115456
2010-10-03 01:12:20 +00:00
f70b4e0c2e
Implement a very basic PIC case.
...
llvm-svn: 115454
2010-10-03 00:46:57 +00:00
4756bbeba0
fix a regression introduced in r115243, in which the instruction
...
backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
llvm-svn: 115422
2010-10-02 21:32:15 +00:00
a2f2c27b20
actually, move the elf tests into the existing elf dir.
...
llvm-svn: 115416
2010-10-02 18:53:48 +00:00
7b1638b40b
consolidate ELF tests into asmparser tests.
...
llvm-svn: 115415
2010-10-02 18:52:57 +00:00
fbae9435c9
move ARM MC tests up one level.
...
llvm-svn: 115414
2010-10-02 18:52:05 +00:00
bf73fe5e8d
Need to specify SSE4 for machines which don't have SSE4. The code checked for is generated by SSE4. Otherwise, we get something else.
...
llvm-svn: 115352
2010-10-01 21:39:35 +00:00
13a642da0b
Now that the profitable bits of EnableFullLoadPRE have been enabled by default, rip out the remainder.
...
Anyone interested in more general PRE would be better served by implementing it separately, to get real
anticipation calculation, etc.
llvm-svn: 115337
2010-10-01 20:02:55 +00:00
d3fe5fa5d1
Fix code gen crash reported in PR 8235. We still lose debug info for the unused argument here. This is a known limitation recorded debuginfo-tests/trunk/dbg-declare2.ll function 'f6' test case.
...
llvm-svn: 115323
2010-10-01 19:00:44 +00:00
a39904e6b9
We must check for something.
...
llvm-svn: 115309
2010-10-01 10:20:10 +00:00
0e5e4b7b76
Disable tests until I can figure out why they're failing on just two machines but not others.
...
llvm-svn: 115308
2010-10-01 10:01:10 +00:00
b3a1022572
Try adding an mtriple.
...
llvm-svn: 115307
2010-10-01 09:40:50 +00:00
56f7cd255b
Zap some redundant 'ori $?, $?, 0' from SPU.
...
Also remove some code that died in the process.
One now non-existant ori is checked for.
llvm-svn: 115306
2010-10-01 09:20:01 +00:00
3b2b1e7942
FileCheck-ize this test.
...
llvm-svn: 115304
2010-10-01 08:55:48 +00:00
9b6853c6eb
FileCheck-ize this test.
...
llvm-svn: 115303
2010-10-01 08:50:12 +00:00
c663a67384
fix PR8267 - Instcombine shouldn't optimizer away volatile memcpy's.
...
llvm-svn: 115296
2010-10-01 05:51:02 +00:00
98e82678bd
upgrade this test.
...
llvm-svn: 115295
2010-10-01 05:47:16 +00:00
a205055857
fix rdar://8494845 + PR8244 - a miscompile exposed by my patch in r101350
...
llvm-svn: 115294
2010-10-01 05:36:09 +00:00
f419de0852
One more +sse2.
...
llvm-svn: 115293
2010-10-01 05:08:18 +00:00
4ca7bb52d0
move X86 subdir up a level
...
llvm-svn: 115292
2010-10-01 04:32:20 +00:00
bb6b961867
Mark all these as needing SSE2. Should fix PPC and
...
maybe even Linux.
llvm-svn: 115291
2010-10-01 04:17:55 +00:00
ab60ae3cf3
Disable these tests for now; it's not obvious why they fail on Linux.
...
llvm-svn: 115257
2010-10-01 00:59:21 +00:00
c6f17f7420
Make test not sensitive to register choice.
...
llvm-svn: 115250
2010-10-01 00:16:17 +00:00
dd224d2333
Massive rewrite of MMX:
...
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
2010-09-30 23:57:10 +00:00
bb995ae261
test/CodeGen/X86/sibcall.ll: Add explicit triplets and remove XFAIL: apple-darwin8.
...
llvm-svn: 115215
2010-09-30 22:02:06 +00:00
3170a25a84
We do want to allow LoadPRE to perform LICM-like transformations: we already consider PHI nodes to be negligible for
...
code size (making this transform code size neutral), and it allows us to hoist values out of loops, which is always
a good thing.
llvm-svn: 115205
2010-09-30 20:53:04 +00:00
eb12f49fb7
Try again to disable critical edge splitting in CodeGenPrepare.
...
The bug that broke i386 linux has been fixed in r115191.
llvm-svn: 115204
2010-09-30 20:51:52 +00:00
f987d5ea1c
Factor some logic into ShouldRelocOnSymbol. This simplifies the code and
...
fixes some cases where we were producing relocations with at symbol that
should use a section instead.
llvm-svn: 115194
2010-09-30 20:18:35 +00:00
665aa6efcc
When isel is emitting instructions for an x86 target without CMOV, the CFG is
...
edited during emission.
If the basic block ends in a switch that gets lowered to a jump table, any
phis at the default edge were getting updated wrong. The jump table data
structure keeps a pointer to the header blocks that wasn't getting updated
after the MBB is split.
This bug was exposed on 32-bit Linux when disabling critical edge splitting in
codegen prepare.
The fix is to uipdate stale MBB pointers whenever a block is split during
emission.
llvm-svn: 115191
2010-09-30 19:44:31 +00:00
1dee57fb7d
more cleanups.
...
llvm-svn: 115178
2010-09-30 17:29:05 +00:00
288a5f9652
merge and clean up tests.
...
llvm-svn: 115177
2010-09-30 17:24:05 +00:00
60217e765e
merge two tests.
...
llvm-svn: 115175
2010-09-30 17:18:22 +00:00
41a0cd14b7
rename test
...
llvm-svn: 115174
2010-09-30 17:16:49 +00:00
ea226b24ff
generalize test.
...
llvm-svn: 115172
2010-09-30 17:15:42 +00:00
28307d1a1e
rename test.
...
llvm-svn: 115171
2010-09-30 17:14:55 +00:00
45a52f3c34
merge two tests.
...
llvm-svn: 115170
2010-09-30 17:14:30 +00:00
73a7caee4b
preemptively add the rest of the non-n fpstack instructions.
...
llvm-svn: 115168
2010-09-30 17:11:29 +00:00
28b3b43fb4
merge two tests.
...
llvm-svn: 115165
2010-09-30 17:05:37 +00:00
1e9e49f421
fix this to not be completely broken.
...
llvm-svn: 115164
2010-09-30 17:04:59 +00:00
c8f0e29b5e
update, unxfail, fix bogus encodings.
...
llvm-svn: 115163
2010-09-30 17:03:20 +00:00
a9e913e139
update and unxfail
...
llvm-svn: 115162
2010-09-30 17:00:53 +00:00
ccf2c765f0
unxfail this by fixing syntactic differences.
...
llvm-svn: 115161
2010-09-30 16:59:28 +00:00
4373badcdf
implement support for finit, PR8258
...
llvm-svn: 115156
2010-09-30 16:42:53 +00:00
adc0dbe470
add support for fstcw, PR8259
...
llvm-svn: 115154
2010-09-30 16:39:29 +00:00
efbdbe5565
Move logic of determining ELF entsize from the .s printer to initialization
...
time. That way, the EntrySize field is initialized for other code paths,
namely, the .ll -> .o code path.
llvm-svn: 115141
2010-09-30 05:59:22 +00:00
9d98ac645e
Add another test that now passes.
...
llvm-svn: 115137
2010-09-30 04:22:07 +00:00
70d6e0e0ff
Correctly produce R_X86_64_32 or R_X86_64_32S.
...
With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
llvm-svn: 115134
2010-09-30 03:11:42 +00:00
645f6c2bef
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
...
Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
2010-09-30 02:45:56 +00:00
b96b2d8e4d
Have ELFAsmParser.cpp use the already parsed "Size" (entry size) when
...
constructing a section. Test for a few cases also included.
llvm-svn: 115132
2010-09-30 02:41:46 +00:00
2ebaee9c75
Make it possible for the MCObjectWriter to decide if a given fixup is fully
...
resolved or not. Different object files have different restrictions and
different native assemblers have different idiosyncrasies we want to emulate
for now.
Move the existing MachO logic to the new place and implement an ELF one that
gets fixups to globals right.
llvm-svn: 115131
2010-09-30 02:22:20 +00:00
2b76c66fd6
Add constant folding for strspn and strcspn to SimplifyLibCalls.
...
llvm-svn: 115116
2010-09-30 00:58:35 +00:00
38d22f69fc
Add strpbrk folding to SimplifyLibCalls.
...
llvm-svn: 115111
2010-09-29 23:52:12 +00:00
8e861d7eee
Simplify the loop in StrChrOptimizer. FileCheckize test.
...
llvm-svn: 115095
2010-09-29 22:29:12 +00:00
824645abc9
Teach SimplifyLibCalls how to optimize strrchr.
...
llvm-svn: 115091
2010-09-29 21:50:51 +00:00
95ae73c394
Generalize DISubprogram element to encode various flags instead of just one boolean for isArtificial.
...
This is a backword compatible change.
llvm-svn: 115084
2010-09-29 21:04:46 +00:00
99c985c37d
Fix PR8247: JumpThreading can cause a block to become unreachable while still having predecessor, if it is part of a self-loop.
...
Because of this, we cannot use the Simplify* APIs, as they can assert-fail on unreachable code. Since it's not easy to determine
if a given threading will cause a block to become unreachable, simply defer simplifying simplification to later InstCombine and/or
DCE passes.
llvm-svn: 115082
2010-09-29 20:34:41 +00:00
0aea752f6d
Remove PointerTracking tests.
...
llvm-svn: 115072
2010-09-29 19:20:35 +00:00
2b43c1cf42
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
...
llvm-svn: 115061
2010-09-29 18:39:16 +00:00
97bf273870
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
...
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
llvm-svn: 115047
2010-09-29 17:54:10 +00:00
53f0bf194a
Move "local commons" to the end of .bss to match the gnu as behavior.
...
llvm-svn: 115037
2010-09-29 14:52:01 +00:00
68e05d404a
Add a test that I forgot to add with a previous commit.
...
llvm-svn: 115036
2010-09-29 14:40:49 +00:00
c2eb72dc2a
do not compare actual branch labels; this may fix llvm-gcc-x86_64-darwin10-cross-mingw32 buildbot too
...
llvm-svn: 115034
2010-09-29 10:45:43 +00:00
d36e3e8850
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
...
added some doxygen on the way
llvm-svn: 115033
2010-09-29 10:12:08 +00:00
8f7851d2b4
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
...
llvm-svn: 115029
2010-09-29 05:05:03 +00:00
52e6020883
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
...
llvm-svn: 115027
2010-09-29 04:55:40 +00:00
822dc48c3a
MC-COFF: Fix test. IMAGE_SYM_CLASS_LABEL should never have been emitted.
...
llvm-svn: 115024
2010-09-29 03:59:25 +00:00
5da7f9fcfd
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
...
order as cctools for diffability.
llvm-svn: 115022
2010-09-29 03:43:43 +00:00
a4e1c74947
implement support for 32-bit address operands in 64-bit mode, which
...
are defined to emit the 0x67 prefix byte. rdar://8482675
llvm-svn: 115021
2010-09-29 03:33:25 +00:00
f60062fd55
add basic avx support to the disassembler, also teach it about ssmem/sdmem
...
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
llvm-svn: 115019
2010-09-29 02:57:56 +00:00
ff3a3930a0
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
...
Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
llvm-svn: 115018
2010-09-29 02:36:32 +00:00
ef1c2fc305
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
...
llvm-svn: 115017
2010-09-29 02:24:57 +00:00
a63292a3ca
implement rdar://8456378 and PR7557 - support for the fstsw,
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an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
cc91601211
And remove r114997's test.
...
llvm-svn: 115003
2010-09-28 23:24:18 +00:00
b0b2c57149
Revert r114997. It was causing a failure on darwin10-selfhost.
...
llvm-svn: 115002
2010-09-28 23:11:55 +00:00
d848beb1e5
Fix a FIXME. _foo.eh symbols are currently always exported so that the linker
...
knows about them. This is not necessary on 10.6 and later.
llvm-svn: 114997
2010-09-28 22:36:56 +00:00
a3181e2d79
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
...
cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
llvm-svn: 114995
2010-09-28 21:57:50 +00:00
81bdc93bbb
User proper libcall names & condcodes while compiling for ARM EABI.
...
Patch by Evzen Muller!
llvm-svn: 114991
2010-09-28 21:39:26 +00:00
88af7d00fc
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
...
Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
llvm-svn: 114973
2010-09-28 18:32:13 +00:00
0ab27ea44f
Add target triple info to these tests to make the results comparable when
...
hosted on different platforms.
llvm-svn: 114965
2010-09-28 17:10:36 +00:00
01d20a76fe
On elf, undefined symbols can start with .L.
...
llvm-svn: 114958
2010-09-28 16:19:11 +00:00
3dc97324c1
Add a command line option "-arm-strict-align" to disallow unaligned memory
...
accesses for ARM targets that would otherwise allow it. Radar 8465431.
llvm-svn: 114941
2010-09-28 04:09:35 +00:00
96bfb50c03
Write relocations in the end of the file. This matches what gas does and
...
makes files easier to diff.
llvm-svn: 114898
2010-09-27 22:04:54 +00:00
9ca41113f6
Make sure .text doesn't produce extra alignment.
...
llvm-svn: 114895
2010-09-27 21:40:27 +00:00
1083573796
Don't try to constant fold libm functions with non-finite arguments.
...
Usually we wouldn't do this anyway because llvm_fenv_testexcept would return an
exception, but we have seen some cases where neither errno nor fenv detect an
exception on arm-linux.
llvm-svn: 114893
2010-09-27 21:29:20 +00:00
d116d8a4e9
MC/AsmParser: Handle exponents in floating point literals.
...
llvm-svn: 114861
2010-09-27 20:12:52 +00:00
415a7a6fec
Revert "Disable codegen prepare critical edge splitting. Machine instruction passes now"
...
This reverts revision 114633. It was breaking llvm-gcc-i386-linux-selfhost.
It seems there is a downstream bug that is exposed by
-cgp-critical-edge-splitting=0. When that bug is fixed, this patch can go back
in.
Note that the changes to tailcallfp2.ll are not reverted. They were good are
required.
llvm-svn: 114859
2010-09-27 18:43:48 +00:00
4f3443e74d
Explicitly disable CGP critical edge splitting for this test so it won't break
...
by reenabling it temporarily.
llvm-svn: 114858
2010-09-27 18:43:43 +00:00
f2a279b902
Don't depend on basic block numbering.
...
llvm-svn: 114857
2010-09-27 18:43:40 +00:00
d628377a2d
MC-COFF: Drop empty sections, and label symbols. Convert relocations
...
targeted at symbols into relocations relative to the containing section.
Patch by Nathan Jeffords!
llvm-svn: 114823
2010-09-27 08:58:26 +00:00
b6a7f97c88
yet more aliases.
...
llvm-svn: 114822
2010-09-27 07:24:57 +00:00
882626cd5b
add a couple more aliases, rdar://8456378
...
llvm-svn: 114821
2010-09-27 07:21:41 +00:00
972c60d821
fix rdar://8470918 - llvm-mc can't assemble smovl
...
llvm-svn: 114819
2010-09-27 07:11:53 +00:00
ff0062af62
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.
...
My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd. Instruction set orthogonality is overrated or
something.
llvm-svn: 114818
2010-09-27 07:08:21 +00:00
9f06f911d1
the latest assembler that runs on powerpc 10.4 machines doesn't
...
support aligned comm. Detect when compiling for 10.4 and don't
emit an alignment for comm. THis will hopefully fix PR8198.
llvm-svn: 114817
2010-09-27 06:44:54 +00:00
4f59cbfb66
implement support for 'clr' alias. This is part of rdar://8416805,
...
but balrog was wanting it on irc.
llvm-svn: 114809
2010-09-27 04:23:03 +00:00
d6142976de
Add test case for PTX ret instruction
...
llvm-svn: 114789
2010-09-25 07:49:54 +00:00
299479020a
Add ret instruction to PTX backend
...
llvm-svn: 114788
2010-09-25 07:46:17 +00:00
75d65b9a03
Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put
...
symbols defined in merge sections in independent atoms.
llvm-svn: 114786
2010-09-25 05:42:19 +00:00
b590a927cd
LoadPRE was not properly checking that the load it was PRE'ing post-dominated the block it was being hoisted to.
...
Splitting critical edges at the merge point only addressed part of the issue; it is also possible for non-post-domination
to occur when the path from the load to the merge has branches in it. Unfortunately, full anticipation analysis is
time-consuming, so for now approximate it. This is strictly more conservative than real anticipation, so we will miss
some cases that real PRE would allow, but we also no longer insert loads into paths where they didn't exist before. :-)
This is a very slight net positive on SPEC for me (0.5% on average). Most of the benchmarks are largely unaffected, but
when it pays off it pays off decently: 181.mcf improves by 4.5% on my machine.
llvm-svn: 114785
2010-09-25 05:26:18 +00:00
cf1f985838
Reapply 114678 and 114667. Reverting them did not fix the bot:
...
http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/69
llvm-svn: 114761
2010-09-24 21:19:03 +00:00
9d06adcf88
Be more precise when trying to XFAIL this tester: http://google1.osuosl.org:8011/builders/llvm-arm-linux
...
llvm-svn: 114755
2010-09-24 20:34:49 +00:00
dbcc4b4d4d
Enable code placement optimization pass for ARM.
...
llvm-svn: 114746
2010-09-24 19:07:23 +00:00
3843bb9d2c
Revert 114678 and 114667 to see if
...
http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost
gets happy.
llvm-svn: 114742
2010-09-24 18:48:08 +00:00
ce17f72c38
MC/AsmParser: Handle a missed case of floating literals in the lexer.
...
llvm-svn: 114733
2010-09-24 17:10:26 +00:00
10d274d874
CMake: Build unittests.
...
llvm-svn: 114725
2010-09-24 09:01:13 +00:00
1444f47deb
Fix whitespace.
...
llvm-svn: 114724
2010-09-24 09:00:56 +00:00
2af1653032
MC/AsmParser: Support .single and .double for embedding floating point literals.
...
- I believe more modern 'gas' supports a more enhanced set of arithmetic on
them, but for now the only thing we can do is emit them as data.
llvm-svn: 114719
2010-09-24 01:59:56 +00:00
7fbbe9a43a
Set alignment operand for NEON VST instructions.
...
llvm-svn: 114709
2010-09-23 23:42:37 +00:00
9eeb890172
Set alignment operand for NEON VLD instructions.
...
llvm-svn: 114696
2010-09-23 21:43:54 +00:00
f458f04eb1
Correctly handle weak undefined symbols. Before we would get a invalid binding
...
(2 == STB_WEAK | STB_GLOBAL).
llvm-svn: 114690
2010-09-23 19:55:14 +00:00
48e108753b
Represent relocations against local symbols as relocations against the section
...
they are in. Both ways should be equivalent, but gas produces relocations
against the section.
Roman wrote the patch, I added the test.
llvm-svn: 114667
2010-09-23 17:25:18 +00:00
3aecb15f0a
Fix llvm-extract so that it changes the linkage of all GlobalValues to
...
"external" even when doing lazy bitcode loading. This was broken because
a function that is not materialized fails the !isDeclaration() test.
llvm-svn: 114666
2010-09-23 17:25:06 +00:00
794aaa79e2
Disable codegen prepare critical edge splitting. Machine instruction passes now
...
break critical edges on demand.
llvm-svn: 114633
2010-09-23 06:55:34 +00:00
0d2c07cf58
Fix llvm-extract -delete's lazy loading to materialize the functions that
...
will not be deleted, rather than the ones that will.
llvm-svn: 114614
2010-09-23 00:33:13 +00:00
3231d13ddd
A select between a constant and zero, when fed by a bit test, can be efficiently
...
lowered using a series of shifts.
Fixes <rdar://problem/8285015>.
llvm-svn: 114599
2010-09-22 22:58:22 +00:00
bbb9287080
Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.
...
llvm-svn: 114597
2010-09-22 22:35:21 +00:00
dee12d8110
Avoid some Mach-O specific alignment being done on ELF.
...
llvm-svn: 114594
2010-09-22 22:27:05 +00:00
9bac6cb544
Correctly align bss.
...
llvm-svn: 114556
2010-09-22 17:43:04 +00:00
922f13ce2e
llvmc: Support '-emit-llvm -S' with -opt.
...
llvm-svn: 114541
2010-09-22 09:00:41 +00:00
415624cf3f
fix rdar://8456371 - Handle commutable instructions written backward.
...
llvm-svn: 114536
2010-09-22 06:26:39 +00:00
bd85725341
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
...
x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
llvm-svn: 114534
2010-09-22 05:49:14 +00:00
37fc469f88
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
...
Teaching the code generator about CR8-15, how to rex them up, etc.
llvm-svn: 114533
2010-09-22 05:29:50 +00:00
2bb9504d1a
fix rdar://8456417 - llvm-mc can't do basic math
...
llvm-svn: 114532
2010-09-22 05:05:16 +00:00
9dfd2e354e
add the missing aliases for fp stack cmovs, rdar://8456391
...
llvm-svn: 114531
2010-09-22 04:56:20 +00:00
8a236b63d8
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
...
llvm-svn: 114529
2010-09-22 04:39:11 +00:00
1261b81e82
Fix rdar://8456364 - llvm-mc rejects '%CS'
...
llvm-svn: 114528
2010-09-22 04:11:10 +00:00
39cf8deded
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'
...
-This line, and those below, will be ignored--
M test/MC/AsmParser/X86/x86_instructions.s
M lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm-svn: 114527
2010-09-22 04:04:03 +00:00
a91e510f94
fix rdar://8456361 - llvm-mc rejects 'rep movsd'
...
llvm-svn: 114526
2010-09-22 03:50:32 +00:00
505af598d0
linux has a different stack alignment than the mac, relax this a bit.
...
llvm-svn: 114519
2010-09-22 00:46:26 +00:00
54e5329545
give VZEXT_LOAD a memory operand, it now works with segment registers.
...
llvm-svn: 114515
2010-09-22 00:34:38 +00:00
07827ba978
revert r114386 now that address modes work correctly, we get a nice
...
call through gs-relative memory now.
llvm-svn: 114510
2010-09-22 00:11:31 +00:00
e479e9643b
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
...
llvm-svn: 114508
2010-09-21 23:59:42 +00:00
0cefa51114
filecheckize
...
llvm-svn: 114507
2010-09-21 23:57:27 +00:00
d757c88bba
OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
...
llvm-svn: 114506
2010-09-21 23:49:07 +00:00
61158f98ab
Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
...
irrelevant, but add a new test for the new, improved functionality.
llvm-svn: 114494
2010-09-21 22:51:46 +00:00
d92f42d1d0
Use FileCheck
...
llvm-svn: 114475
2010-09-21 20:50:32 +00:00
f4b1a5bdc4
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
...
(sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.
This fixes <rdar://problem/8449754>.
llvm-svn: 114460
2010-09-21 18:41:19 +00:00
ed79d5f24d
llvmc: Allow multiple output languages.
...
llvm-svn: 114433
2010-09-21 14:59:42 +00:00
bb0a1c44bf
fix rdar://8453210, a crash handling a call through a GS relative load.
...
For now, just disable folding the load into the call.
llvm-svn: 114386
2010-09-21 03:37:00 +00:00
f0591c1642
Implement support for .local and its "interesting" interactions with .comm.
...
llvm-svn: 114382
2010-09-21 00:24:38 +00:00
f3e9a48584
Enable machine sinking critical edge splitting. e.g.
...
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
%z = select i1 %c, double %a, double %y
ret double %z
}
Was:
_foo:
divsd LCPI0_0(%rip), %xmm0
testb $1, %dil
jne LBB0_2
movaps %xmm1, %xmm0
LBB0_2:
ret
Now:
_foo:
testb $1, %dil
je LBB0_2
divsd LCPI0_0(%rip), %xmm0
ret
LBB0_2:
movaps %xmm1, %xmm0
ret
This avoids the divsd when early exit is taken.
rdar://8454886
llvm-svn: 114372
2010-09-20 22:52:00 +00:00
5e4734245d
CombinerAA is now reordering these stores.
...
llvm-svn: 114354
2010-09-20 20:56:29 +00:00
272ff94916
When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore,
...
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.
This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.
llvm-svn: 114348
2010-09-20 20:39:59 +00:00
94dfd6fc4f
Simplify ARM callee-saved register handling by removing the distinction
...
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.
For example, previously we would generate code like:
push {r4, r5, r6, r7, lr}
add r7, sp, #12
stmdb sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
push {r4, r5, r6, r7, r8, r10, r11, lr}
add r7, sp, #12
rdar://8445635
llvm-svn: 114340
2010-09-20 19:32:20 +00:00
32ab4558fe
Produce a R_X86_64_32 when the value is >=0.
...
llvm-svn: 114339
2010-09-20 19:20:47 +00:00
b912c27fc9
test/CodeGen/X86: Add explicit triplet -mtriple=i686-linux to 3 tests incompatible to Win32 codegen.
...
r114297 raises 3 failures. They might fail also on mingw.
llvm-svn: 114317
2010-09-19 21:58:55 +00:00
dbb199d89b
Add the exit instruction to the PTX target.
...
Patch by Che-Liang Chiou <clchiou@gmail.com>!
llvm-svn: 114294
2010-09-18 18:52:28 +00:00
57e599a82a
Make sure the STT_FILE symbol is the first one in the symbol table.
...
llvm-svn: 114285
2010-09-18 15:03:21 +00:00
b92b13d8a0
Invert the logic of reachesChainWithoutSideEffects(). What we want to check is that there is
...
NO path to the destination containing side effects, not that SOME path contains no side effects.
In practice, this only manifests with CombinerAA enabled, because otherwise the chain has little
to no branching, so "any" is effectively equivalent to "all".
llvm-svn: 114268
2010-09-18 04:45:14 +00:00
15829c6c4c
Add test that was missing in my previous commit.
...
llvm-svn: 114248
2010-09-18 00:37:27 +00:00
49c15c0f9f
Attempt to XFAIL this test on arm-linux, which is inexplicably failing.
...
llvm-svn: 114241
2010-09-18 00:04:37 +00:00
de636ca9a8
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
...
llvm-svn: 114240
2010-09-17 23:48:07 +00:00
cb6db98897
Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
...
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert. Radar 8407927.
llvm-svn: 114233
2010-09-17 22:59:05 +00:00
7a6c37d3e7
Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
...
and shift instructions on ARM. Update the tests to match.
llvm-svn: 114230
2010-09-17 22:36:38 +00:00
e53ab6dffc
Teach machine sink to
...
1) Do forward copy propagation. This makes it easier to estimate the cost of the
instruction being sunk.
2) Break critical edges on demand, including cases where the value is used by
PHI nodes.
Critical edge splitting is not yet enabled by default.
llvm-svn: 114227
2010-09-17 22:28:18 +00:00
6d800f88da
Update tests to handle MC-inst instruction printing of shift operations. The
...
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.
llvm-svn: 114221
2010-09-17 21:58:46 +00:00
4a5e54021a
FileCheck-ize
...
llvm-svn: 114218
2010-09-17 21:46:16 +00:00
20da4e360b
Move thumb2 tests to the thumb2 directory
...
llvm-svn: 114206
2010-09-17 20:34:09 +00:00
9b0cd20f72
tweak test to check instructions rather than relying on the comment string
...
llvm-svn: 114204
2010-09-17 20:27:26 +00:00
f3a9c464b4
Fix this test to avoid an "inexact" fold.
...
llvm-svn: 114202
2010-09-17 20:25:43 +00:00
534db8a5c8
Avoid emitting a PIC base register if no PIC addresses are needed.
...
This fixes rdar://8396318.
llvm-svn: 114201
2010-09-17 20:24:24 +00:00
f3ceecec7e
tweak test to check instructions rather than relying on the comment string
...
llvm-svn: 114200
2010-09-17 20:21:03 +00:00
c18a460adc
tweak test to check instructions rather than relying on the comment string
...
llvm-svn: 114199
2010-09-17 20:17:41 +00:00
695312637c
Fix this test so that folding doesn't depend on a potentially
...
"inexact" result.
llvm-svn: 114198
2010-09-17 20:15:53 +00:00
cea0a8d7ae
fix rdar://8444631 - encoder crash on 'enter'
...
What a weird instruction.
llvm-svn: 114190
2010-09-17 18:02:29 +00:00
35a7a0ee2e
MC/Mach-O/i386: Fix a crash in relocation handling.
...
llvm-svn: 114176
2010-09-17 15:21:50 +00:00
d890a54353
tests/CMakeLists.txt: use `configure_file' instead of `sed'.
...
The Windows users will appreciate this.
llvm-svn: 114158
2010-09-17 03:22:21 +00:00
55f16678e4
MC/AsmParser: Add support for 'a + 4@GOTPCREL' and friends, by reconsing the
...
expression to include the modifier.
- Gross, but this a corner case we don't expect to see often in practice, but
it is worth accepting.
- Also improves diagnostics on invalid modifiers.
llvm-svn: 114154
2010-09-17 02:47:07 +00:00
18fa17cf3d
Fix the folding of floating-point math library calls, like sin(infinity),
...
so that it detects errors on platforms where libm doesn't set errno.
It's still subject to host libm details though.
llvm-svn: 114148
2010-09-17 01:38:06 +00:00
871d0b1b1c
If FE forgot to provide a file name (usually it uses "stdin" as name in such situation) then make one up to ensure that debug info is not malformed.
...
llvm-svn: 114119
2010-09-16 20:57:49 +00:00
74d320db97
fix rdar://8438816 - unrecognized 'fildq' instruction
...
llvm-svn: 114116
2010-09-16 20:46:38 +00:00
44bf266111
Print the address of sections as 0 and create the metadata sections in the
...
same order as gnu as.
llvm-svn: 114109
2010-09-16 19:46:31 +00:00
20154b3ed4
Add missing RUN line to this test.
...
llvm-svn: 114106
2010-09-16 18:46:23 +00:00
f95f59a0c2
When substituting sunkaddrs into indirect arguments an asm, we were
...
walking the asm arguments once and stashing their Values. This is
wrong because the same memory location can be in the list twice, and
if the first one has a sunkaddr substituted, the stashed value for the
second one will be wrong (use-after-free). PR 8154.
llvm-svn: 114104
2010-09-16 18:30:55 +00:00
140296f5c0
It is possible, under specific circumstances involving ptrtoint ConstantExpr's, for LVI to end up trying to merge
...
a Constant into a ConstantRange. Handle this conservatively for now, rather than asserting. The testcase is
more complex that I would like, but the manifestation of the problem is sensitive to iteration orders and the state of the
LVI cache, and I have not been able to reproduce it with manually constructed or simplified cases.
Fixes PR8162.
llvm-svn: 114103
2010-09-16 18:28:33 +00:00
94532cb297
Fix PR8161, in which an unreachable loop causes recursive instruction simplification to try
...
to replace an instruction with itself. Add a predicate to the simplifier to prevent this case.
llvm-svn: 114097
2010-09-16 17:42:36 +00:00
f7f433200b
Make sure that names like .note.GNU-stack are accepted as valid section names.
...
llvm-svn: 114091
2010-09-16 17:05:55 +00:00
922e3f454b
Add support for the .zero directive.
...
llvm-svn: 114077
2010-09-16 15:03:59 +00:00
c0e9b8d8bb
Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
...
This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.
Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.
llvm-svn: 114074
2010-09-16 12:29:33 +00:00
196841144d
add a test of an edge case value for the FP immediate (needs all digits of
...
precision)
llvm-svn: 114028
2010-09-15 21:52:13 +00:00
f667d929ce
Add a InitSections method to the streamer interface.
...
The ELF implementation now creates text, data and bss to match the gnu as
behavior.
The text streamer still has the old MachO specific behavior since
the testsuite checks that it will error when a directive is given
before a setting the current section for example.
A nice benefit is that -n is not required anymore when producing
ELF files.
llvm-svn: 114027
2010-09-15 21:48:40 +00:00
27ab5fbd2b
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
...
moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
llvm-svn: 114021
2010-09-15 21:04:54 +00:00
ab3a128582
PR7959: Handle negative scales in GEPs correctly in BasicAA for non-64-bit
...
targets.
llvm-svn: 114015
2010-09-15 20:08:03 +00:00
660d7ecf32
Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
...
encountered while building llvm-gcc for arm. This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.
llvm-svn: 113983
2010-09-15 17:12:08 +00:00
9ae4b271f2
the darwin9-powerpc buildbot keeps consistently crashing,
...
backing out following to get it back to green,
so I can investigate in peace:
svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm-svn: 113980
2010-09-15 16:53:07 +00:00
0c99d12208
llvmc: make -x work with unknown suffixes.
...
llvm-svn: 113972
2010-09-15 15:20:41 +00:00
ee7e6f42f8
lcall and ljmp always default to lcalll and ljmpl. This finally
...
wraps up r8418316
llvm-svn: 113949
2010-09-15 05:30:20 +00:00
09bfe645f6
apparently jmpl $1,$2 is an alias for ljmpl, similiarly
...
for call. Add this.
llvm-svn: 113948
2010-09-15 05:25:21 +00:00
6757eae45e
Disambiguate lcall/ljmp to the 32-bit version. This happens
...
even in 64-bit mode apparently.
llvm-svn: 113945
2010-09-15 05:14:54 +00:00
5be87c619b
fix the encoding of sldt GR16 to have the 0x66 prefix, and
...
add sldt GR32, which isn't documented in the intel manual
but which gas accepts. Part of rdar://8418316
llvm-svn: 113938
2010-09-15 04:45:10 +00:00
6b40b0def1
implement aliases for shld/shrd, part of rdar://8418316
...
llvm-svn: 113937
2010-09-15 04:37:18 +00:00
4bd21710b6
fix rdar://8431880 - rcl/rcr with no shift amount not recognized
...
llvm-svn: 113936
2010-09-15 04:33:27 +00:00
81ce173860
add various broken forms of fnstsw. I didn't add the %rax
...
version because it adds a prefix and makes even less sense
than the other broken forms. This wraps up rdar://8431422
llvm-svn: 113932
2010-09-15 04:15:16 +00:00
7df35dbd19
add some aliases for f[u]comi, part of rdar://8431422
...
llvm-svn: 113930
2010-09-15 04:08:38 +00:00
4dbcba0082
add a bunch of aliases for fp operations with no operand,
...
rdar://8431422
llvm-svn: 113929
2010-09-15 04:04:33 +00:00
46d4cc2ef7
test: Fix coff-dump section array indicies to 1 based to match file format.
...
llvm-svn: 113928
2010-09-15 03:58:51 +00:00
5d2c9acbdf
Tabs to spaces
...
llvm-svn: 113927
2010-09-15 03:58:39 +00:00
8ae7922a89
Cleanup coff-dump.py
...
llvm-svn: 113926
2010-09-15 03:58:24 +00:00
67e534505d
fix PR8144, a bug where constant merge would merge globals marked
...
attribute(used).
llvm-svn: 113911
2010-09-15 00:30:11 +00:00
c7cf42d80b
Reapply r113875 with additional cleanups.
...
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."
Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.
llvm-svn: 113903
2010-09-14 23:54:06 +00:00
5f2311dc29
add a terrible hack to allow out with dx is parens, a gas bug.
...
This fixes PR8114
llvm-svn: 113894
2010-09-14 23:34:29 +00:00
f6fe577e88
Remove dead option from tests.
...
llvm-svn: 113855
2010-09-14 21:03:40 +00:00
00e34f4b32
forgot the testcase change for r113839
...
llvm-svn: 113840
2010-09-14 09:30:17 +00:00
5dbe800203
test for and-tst peephole optimization
...
documents the status-quo with its opportunities
llvm-svn: 113838
2010-09-14 08:50:43 +00:00
f1144f0929
fix PR8102, a case where we'd copyValue from a value that we already
...
deleted. Fix this by doing the copyValue's before we delete stuff!
The testcase only repros the problem on my system with valgrind.
llvm-svn: 113820
2010-09-14 00:19:00 +00:00
b1248ffe9d
Basic smoke test for new x86mmx type.
...
llvm-svn: 113783
2010-09-13 21:01:36 +00:00
fe12f23024
Add a reduced testcase for the infinite loop fixed in r113763.
...
llvm-svn: 113770
2010-09-13 18:28:40 +00:00
c237a849e3
Re-apply r113679, which was reverted in r113720, which added a paid of new instcombine transforms
...
to expose greater opportunities for store narrowing in codegen. This patch fixes a potential
infinite loop in instcombine caused by one of the introduced transforms being overly aggressive.
llvm-svn: 113763
2010-09-13 17:59:27 +00:00
df65e14397
Spelling fixes in comments.
...
llvm-svn: 113746
2010-09-13 13:32:22 +00:00
26abd3e0c2
Revert 113679, it was causing an infinite loop in a testcase that I've sent
...
on to Owen.
llvm-svn: 113720
2010-09-12 06:09:23 +00:00
1bbb14ab8f
add a missed cmov alias, part of rdar://8416805
...
llvm-svn: 113693
2010-09-11 17:08:22 +00:00
3340c3e86c
add support for all the setCC aliases. Part of rdar://8416805
...
llvm-svn: 113692
2010-09-11 17:06:05 +00:00
12d73d1f18
Add support for leb128 of absolute expressions.
...
llvm-svn: 113691
2010-09-11 16:45:15 +00:00
b47c042e09
add support for pushfd/popfd which are aliases for pushfl/popfl.
...
This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors
llvm-svn: 113690
2010-09-11 16:39:16 +00:00
30561aba20
implement rdar://8407928 - support for in/out with a missing "a" register.
...
llvm-svn: 113689
2010-09-11 16:32:12 +00:00
6e321507b6
Add missing single quotes.
...
llvm-svn: 113687
2010-09-11 15:45:48 +00:00
2833e392ab
Change section_data dumping to print hex numbers instead of using
...
python's %r.
llvm-svn: 113685
2010-09-11 15:25:58 +00:00
70f4524427
Invert and-of-or into or-of-and when doing so would allow us to clear bits of the and's mask.
...
This can result in increased opportunities for store narrowing in code generation. Update a number of
tests for this change. This fixes <rdar://problem/8285027>.
Additionally, because this inverts the order of ors and ands, some patterns for optimizing or-of-and-of-or
no longer fire in instances where they did originally. Add a simple transform which recaptures most of these
opportunities: if we have an or-of-constant-or and have failed to fold away the inner or, commute the order
of the two ors, to give the non-constant or a chance for simplification instead.
llvm-svn: 113679
2010-09-11 05:48:06 +00:00
8c35fb0739
Teach InstructionSimplify to fold (A & B) & A -> A & B and (A | B) | A -> A | B.
...
Reassociate does this but it doesn't catch all cases (e.g. if the operands are i1).
llvm-svn: 113651
2010-09-10 22:39:55 +00:00
e26fffc597
Auto-upgrade the magic ".llvm.eh.catch.all.value" global to
...
"llvm.eh.catch.all.value". Only the name needs to be changed.
llvm-svn: 113600
2010-09-10 18:51:56 +00:00
1d6aa46cd7
Fix test so it passes on non-Darwin hosts.
...
llvm-svn: 113577
2010-09-10 06:20:01 +00:00
8617234658
Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
...
to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the operands but forgot to adjust for
the size of D registers. This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.
llvm-svn: 113576
2010-09-10 05:15:04 +00:00
bf4070756f
Teach if-converter to be more careful with predicating instructions that would
...
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
llvm-svn: 113570
2010-09-10 01:29:16 +00:00
e5444a88cd
llvm-mc: Don't crash when using -n and we see a directive before the initial section.
...
- This is annoying, because we have to scatter this check everywhere that could emit real data, but I see no better solution.
llvm-svn: 113552
2010-09-09 22:42:59 +00:00
43325c4a68
llvm-mc: Make sure we exit != 0 if any errors are encountered.
...
llvm-svn: 113551
2010-09-09 22:42:56 +00:00
728941fabc
XFAIL test under valgrind. It is not really our problem if sh is leaking.
...
llvm-svn: 113550
2010-09-09 22:02:13 +00:00
6270515918
Revert r113439, which relaxed the requirement that loops containing calls cannot be unrolled. After some discussion,
...
there seems to be a better way to achieve the same effect.
llvm-svn: 113528
2010-09-09 20:02:23 +00:00
e8501a468c
Add one more pattern to fallback movddup
...
llvm-svn: 113522
2010-09-09 18:48:34 +00:00
db0ddaa50b
tests: XFAIL a handful of tests on the vg_leak builder, so we can get back to
...
green.
llvm-svn: 113491
2010-09-09 15:50:19 +00:00
0a96578ac0
Add an elf-dumper utility.
...
- Output format and some of the code stolen from macho-dump.
- Somewhat incomplete and probably buggy.
- Comes with a very basic test.
llvm-svn: 113488
2010-09-09 15:00:41 +00:00
78617ea13a
Get rid of the last use of -m64 in FrontendC. This solution
...
of checking for either 4 or 8 is not very satisfactory, but
it would catch the original problem (an alignment of 1).
llvm-svn: 113485
2010-09-09 12:57:29 +00:00
11d56c309a
Another test that uses -m64. Here too it looks like it can be
...
removed. Not that the XTARGET wasn't doing anything since it
does nothing without an accompanying XFAIL.
llvm-svn: 113484
2010-09-09 12:48:04 +00:00
e194e0c077
On i386, llvm-gcc cannot be assumed to support -m64. Since these
...
tests pass here (i686-linux and x86-64-linux) without -m64, simply
remove the -m64.
llvm-svn: 113483
2010-09-09 12:43:44 +00:00
4adbaf1843
Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from
...
the VST pseudos. The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.
llvm-svn: 113473
2010-09-09 05:40:26 +00:00
8084dbaf8e
Relax the "don't unroll loops containing calls" rule. Instead, when a loop contains a call, lower the
...
unrolling threshold to the optimize-for-size threshold. Basically, for loops containing calls, unrolling
can still be profitable as long as the loop is REALLY small.
llvm-svn: 113439
2010-09-08 23:10:07 +00:00
28a9c2f89a
fix rdar://8407548, I missed the commuted form of xchg/test without a suffix.
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llvm-svn: 113427
2010-09-08 22:27:05 +00:00
3fe002dfb5
Generalize instcombine's support for combining multiple bit checks into a single test. Patch by Dirk Steinke!
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llvm-svn: 113423
2010-09-08 22:16:17 +00:00
8ead237758
fix bugs in push/pop segment support, rdar://8407242
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llvm-svn: 113422
2010-09-08 22:13:08 +00:00
504d23bd05
Re-enable usage of the ARM base pointer. r113394 fixed the known failures.
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Re-running some nightly testers w/ it enabled to verify.
llvm-svn: 113399
2010-09-08 20:12:02 +00:00
ca2ec95154
Remove ssp from this test.
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llvm-svn: 113392
2010-09-08 19:32:34 +00:00
e542972828
Fix CellSPU vector shuffles, again.
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Some cases of lowering to rotate were miscompiled.
llvm-svn: 113355
2010-09-08 11:53:38 +00:00
2907d2e419
add support for the commuted form of the test instruction, rdar://8018260.
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llvm-svn: 113352
2010-09-08 05:51:12 +00:00
a9ca7837e4
implement proper support for sysret{,l,q}, rdar://8403907
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llvm-svn: 113350
2010-09-08 05:45:34 +00:00
063363fa80
implement the iret suite of instructions properly,
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fixing rdar://8403974
llvm-svn: 113349
2010-09-08 05:38:31 +00:00
086a83afb1
add support for instruction prefixes on the same line as the instruction,
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implementing rdar://8033482 and PR7254.
llvm-svn: 113348
2010-09-08 05:17:37 +00:00
8caea68a4f
gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>.
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Add this to the mc assembler, fixing PR8061
llvm-svn: 113346
2010-09-08 04:53:27 +00:00
4703cb4a96
fix the encoding of the "jump on *cx" family of instructions,
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rdar://8061602
llvm-svn: 113343
2010-09-08 04:30:51 +00:00
261df12f64
disable for the moment while tracking down a few Thumb2-O0 failure that look
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related. (attempt deux, complete w/ test update this time)
llvm-svn: 113333
2010-09-08 02:00:34 +00:00
3f4abf397c
remove these tests for now.
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llvm-svn: 113293
2010-09-07 22:03:44 +00:00
Owen Anderson