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208 Commits

Author SHA1 Message Date
Evan Cheng 8cbbcb1f2f Encode VFP load / store instructions. 
llvm-svn: 59084
 2008-11-11 21:48:44 +00:00
Evan Cheng 38c9a14a88 Encode VFP conversion instructions. 
llvm-svn: 59074
 2008-11-11 19:40:26 +00:00
Evan Cheng ac2af2fdb2 Encode VFP arithmetic instructions. 
llvm-svn: 59016
 2008-11-11 02:11:05 +00:00
Evan Cheng 9f3058f3be Rename isGVNonLazyPtr to isIndirectSym to reflect how it will be used. 
llvm-svn: 58949
 2008-11-10 01:08:07 +00:00
Evan Cheng 98161f5f34 Tell ARMJITInfo if codegen relocation is PIC. It changes how function stubs are generated. 
llvm-svn: 58896
 2008-11-08 07:38:22 +00:00
Evan Cheng bb373c4637 Fix relocation for calls to external symbols. 
llvm-svn: 58893
 2008-11-08 07:22:33 +00:00
Evan Cheng 077c8f8832 Skip over two-address use operands. 
llvm-svn: 58883
 2008-11-08 01:44:13 +00:00
Evan Cheng ffdd91e3b8 Handle ARM machine constantpool entry with non-lazy ptr. 
llvm-svn: 58882
 2008-11-08 01:31:27 +00:00
Evan Cheng ef4d78ba67 More code clean up. 
llvm-svn: 58872
 2008-11-07 22:57:53 +00:00
Evan Cheng 8467e2459a Get PIC jump table working. 
llvm-svn: 58869
 2008-11-07 22:30:53 +00:00
Evan Cheng 7095cd2af2 Jump table JIT support. Work in progress. 
llvm-svn: 58836
 2008-11-07 09:06:08 +00:00
Evan Cheng 98dc53e926 Encode misc arithmetic instructions. 
llvm-svn: 58828
 2008-11-07 01:41:35 +00:00
Evan Cheng 49d665218c Encode extend instructions; more clean up. 
llvm-svn: 58818
 2008-11-06 22:15:19 +00:00
Evan Cheng aa03cd3336 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. 
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
 2008-11-06 17:48:05 +00:00
Evan Cheng 47b546d75f Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
llvm-svn: 58800
 2008-11-06 08:47:38 +00:00
Evan Cheng b870fd8874 Fix so_imm encoding bug; add support for MOVi2pieces. 
llvm-svn: 58790
 2008-11-06 02:25:39 +00:00
Evan Cheng 2686c8fb34 Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls. 
llvm-svn: 58789
 2008-11-06 01:21:28 +00:00
Evan Cheng fd2adbfa28 Encode pic load / store instructions; fix some encoding bugs. 
llvm-svn: 58780
 2008-11-05 23:22:34 +00:00
Evan Cheng 81889d010c Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions. 
llvm-svn: 58764
 2008-11-05 18:35:52 +00:00
Evan Cheng 4eaff40147 Debug output tweak. 
llvm-svn: 58708
 2008-11-04 17:58:53 +00:00
Evan Cheng 6dd08b6604 Handle ARM machine constantpool entries. 
llvm-svn: 58671
 2008-11-04 00:50:32 +00:00
Jim Grosbach 4d0549e3be Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there. 
llvm-svn: 58626
 2008-11-03 18:38:31 +00:00
Evan Cheng 20dbb3bcad Use better data structure for ConstPoolId2AddrMap. 
llvm-svn: 58532
 2008-10-31 19:55:13 +00:00
Evan Cheng 44994e0c77 Actually make debug output understandable. 
llvm-svn: 58529
 2008-10-31 19:15:52 +00:00
Evan Cheng 467e6e8093 Encode PICADD; some code clean up. 
llvm-svn: 58526
 2008-10-31 19:10:44 +00:00
Evan Cheng c696ef9b11 I think we got non-machine specific constpool entries covered. 
llvm-svn: 58474
 2008-10-30 23:43:36 +00:00
Evan Cheng 19d64ba8bf Correct way to handle CONSTPOOL_ENTRY instructions. 
llvm-svn: 58409
 2008-10-29 23:55:43 +00:00
Jim Grosbach ff2b4948ce Support for constant islands in the ARM JIT. 
Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the 
instruction stream.

Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.

For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.

llvm-svn: 58338
 2008-10-28 18:25:49 +00:00
Jim Grosbach c084e84028 Encode the conditional execution predicate when JITing. 
llvm-svn: 57258
 2008-10-07 19:05:35 +00:00
Jim Grosbach 2fb5c3938b Clarify naming and correct conditional so that CMP and CMN instructions get the Rn operand encoded properly 
llvm-svn: 57252
 2008-10-07 17:42:09 +00:00
Jim Grosbach 332ad5e016 Indexing off by one resulted in errant encoding of source register for 
reg->reg moves.

llvm-svn: 57011
 2008-10-03 15:53:56 +00:00
Jim Grosbach af929abc01 NeedStub/DoesntNeedStub logic was reversed, leading to not using a stub 
for global relocations that do need them (libc calls, for example).

llvm-svn: 57010
 2008-10-03 15:52:42 +00:00
Dan Gohman 0d1e9a8e04 Switch the MachineOperand accessors back to the short names like 
isReg, etc., from isRegister, etc.

llvm-svn: 57006
 2008-10-03 15:45:36 +00:00
Jim Grosbach 3dc0a3bce3 Fix typo s/ther/there/ 
llvm-svn: 56924
 2008-10-01 18:16:49 +00:00
Evan Cheng 933b392f65 Duh. Default to ARMCC::AL (always). 
llvm-svn: 56301
 2008-09-18 07:28:19 +00:00
Evan Cheng 7848cfcd77 Fix addrmode1 instruction encodings; fix bx_ret encoding. 
llvm-svn: 56277
 2008-09-17 07:53:38 +00:00
Evan Cheng a5804effed Fix random abort. 
llvm-svn: 56184
 2008-09-13 01:55:59 +00:00
Evan Cheng 380482ac46 Typo. 
llvm-svn: 56182
 2008-09-13 01:44:01 +00:00
Evan Cheng ba28161103 Rely on instruction format to determine so_reg operand for now. 
llvm-svn: 56181
 2008-09-13 01:38:29 +00:00
Evan Cheng 12134701ec Revert 56176. All those instruction formats are still needed. 
llvm-svn: 56180
 2008-09-13 01:35:33 +00:00
Evan Cheng db6571a2c7 Accidentially flipped the condition. 
llvm-svn: 56179
 2008-09-13 01:29:57 +00:00
Evan Cheng 25a39094f8 Add debug dumps. 
llvm-svn: 56178
 2008-09-13 01:15:21 +00:00
Evan Cheng c5c74f36fd Eliminate unnecessary instruction formats. 
llvm-svn: 56176
 2008-09-12 23:15:39 +00:00
Evan Cheng d1424c4eca Addrmode 1 S bit can be dynamically set. Look for CPSR def. 
llvm-svn: 56172
 2008-09-12 22:45:55 +00:00
Evan Cheng 33fa89c6fb Rewrite address mode 1 code emission routines. 
llvm-svn: 56171
 2008-09-12 22:01:15 +00:00
Dan Gohman a79db30d28 Tidy up several unbeseeming casts from pointer to intptr_t. 
llvm-svn: 55779
 2008-09-04 17:05:41 +00:00
Evan Cheng 3be5b728b1 Revamp ARM JIT. 
llvm-svn: 55624
 2008-09-02 06:52:38 +00:00
Anton Korobeynikov 40d67c59d5 Remove bunch of gcc 4.3-related warnings from Target 
llvm-svn: 47369
 2008-02-20 11:22:39 +00:00
Dan Gohman 3a4be0fdef Rename MRegisterInfo to TargetRegisterInfo. 
llvm-svn: 46930
 2008-02-10 18:45:23 +00:00
Chris Lattner 03ad885039 rename TargetInstrDescriptor -> TargetInstrDesc. 
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
 2008-01-07 07:27:27 +00:00
Chris Lattner a98c679de0 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects 
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674
 2008-01-07 01:56:04 +00:00
Chris Lattner a5bb370aa4 Add new shorter predicates for testing machine operands for various types: 
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464
 2007-12-30 23:10:15 +00:00
Chris Lattner 5c4637816e Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm 
llvm-svn: 45453
 2007-12-30 20:49:49 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Raul Herbster 1457b2b3b1 Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly. 
llvm-svn: 41627
 2007-08-30 23:29:26 +00:00
Evan Cheng f7c6effc44 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00
Chris Lattner 396156e00b no email addrs in file headers 
llvm-svn: 39962
 2007-07-17 05:56:43 +00:00
Evan Cheng 9546a5c7de Initial ARM JIT support by Raul Fernandes Herbster. 
llvm-svn: 37926
 2007-07-05 21:15:40 +00:00