5cadccc4ea
Fix a compiler warning about Kind being used uninitialized
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when assertions are disabled.
llvm-svn: 119962
2010-11-22 09:38:00 +00:00
2aeb8b9361
Minor cleanups to a few llvm_unreachable() calls.
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llvm-svn: 119767
2010-11-19 00:27:09 +00:00
2ecfcbd2aa
An 'unreachable' shouldn't have a '0 &&' prefix.
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llvm-svn: 119762
2010-11-19 00:05:15 +00:00
5a97bd873e
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
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Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
llvm-svn: 119760
2010-11-18 23:37:15 +00:00
345b48fcbd
Add binary emission stuff for VLDM/VSTM. This reuses the
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"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.
llvm-svn: 119435
2010-11-17 00:45:23 +00:00
38b469effd
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
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llvm-svn: 119180
2010-11-15 20:47:07 +00:00
63274cbc5d
add fields to the .td files unconditionally, simplifying tblgen a bit.
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Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
8fdd172502
First stab at providing correct Thumb2 encodings, start with adc.
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llvm-svn: 118924
2010-11-12 21:12:40 +00:00
20b6fd7d5d
Start of support for binary emit of 16-it Thumb instructions.
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llvm-svn: 118859
2010-11-11 23:41:09 +00:00
ce2250fba4
Fill out support for Thumb2 encodings of NEON instructions.
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llvm-svn: 118854
2010-11-11 23:12:55 +00:00
99a8cb4875
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
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llvm-svn: 118843
2010-11-11 21:36:43 +00:00
7ffe3b35ac
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
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More tests to come.
llvm-svn: 118819
2010-11-11 19:07:48 +00:00
9d6d77a9f4
Encoding of destination fixup for ARM branch and conditional branch
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instructions.
llvm-svn: 118801
2010-11-11 18:04:49 +00:00
68685e644f
Encoding for ARM LDRSH_POST.
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llvm-svn: 118794
2010-11-11 16:55:29 +00:00
607efcbc3e
ARM STRH encoding information.
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llvm-svn: 118757
2010-11-11 01:09:40 +00:00
cc4a491557
ARM LDM encoding for the mode (ia, ib, da, db) operand.
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llvm-svn: 118736
2010-11-10 23:38:36 +00:00
59002dc973
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
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a left shift by zero.
llvm-svn: 118587
2010-11-09 17:38:15 +00:00
dbfb5edbdb
Add encoder method for ARM load/store shifted register offset operands.
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llvm-svn: 118513
2010-11-09 17:20:53 +00:00
9098714f8b
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
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constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
llvm-svn: 118469
2010-11-09 01:37:15 +00:00
1b83ed5f7c
Revert r118457 and r118458. These won't hold for GPRs.
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llvm-svn: 118462
2010-11-09 00:30:18 +00:00
31b850be15
Get the register and count from the register list operands.
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llvm-svn: 118458
2010-11-08 23:51:20 +00:00
0fb841fd19
Add ARM fixup info for load/store label references. Probably will need a bit of
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tweaking when we start using it for object file emission or JIT, but it's a
start.
llvm-svn: 118221
2010-11-04 01:12:30 +00:00
2eed7a1310
Teach ARM Target to use the tblgen support for generating an MC'ized
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CodeEmitter.
llvm-svn: 118209
2010-11-03 23:52:49 +00:00
49b0c45ecf
trailing whitespace
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llvm-svn: 118199
2010-11-03 22:03:20 +00:00
6552a109bb
Put the PC encoding in the correct bit position.
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llvm-svn: 118151
2010-11-03 04:57:44 +00:00
e84eb99cbb
The MC code couldn't handle ARM LDR instructions with negative offsets:
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
2010-11-03 01:49:29 +00:00
f9eebb58b9
Obsessive formatting changes. No functionality impact.
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llvm-svn: 118103
2010-11-02 22:53:11 +00:00
23436b6530
Omit unused parameter name.
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llvm-svn: 118099
2010-11-02 22:46:04 +00:00
91da9abbee
Simplify the EncodeInstruction method now that a lot of the special case stuff
...
is handled with the MC encoder.
llvm-svn: 118098
2010-11-02 22:44:12 +00:00
603bd8f54c
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
...
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
llvm-svn: 118094
2010-11-02 22:31:46 +00:00
a4b63e19d2
Rename encoder methods to match naming convention.
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llvm-svn: 118093
2010-11-02 22:28:01 +00:00
a83859539f
Add correct encodings for the rest of the vld instructions that we generate.
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llvm-svn: 118053
2010-11-02 20:40:59 +00:00
526ffd57d2
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
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llvm-svn: 117997
2010-11-02 01:24:55 +00:00
f1610f7910
Add aesthetic break.
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llvm-svn: 117986
2010-11-02 00:14:00 +00:00
ad40234eff
Add correct NEON encodings for the "multiple single elements" form of vld.
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llvm-svn: 117984
2010-11-02 00:05:05 +00:00
2ba03aa618
Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME
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for handling the fixup necessary.
llvm-svn: 117978
2010-11-01 23:45:50 +00:00
a3efae35f5
Remove unused function.
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llvm-svn: 117977
2010-11-01 23:40:56 +00:00
7b275105d6
Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
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llvm-svn: 117766
2010-10-30 01:40:16 +00:00
74ef9e184e
Encode the register list operands for ARM mode LDM/STM instructions.
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llvm-svn: 117753
2010-10-30 00:37:59 +00:00
96d828448f
trailing whitespace
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llvm-svn: 117740
2010-10-29 23:21:03 +00:00
58018e62a8
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
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encoder functions.
llvm-svn: 117738
2010-10-29 23:19:55 +00:00
505607e4c6
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
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llvm-svn: 117571
2010-10-28 18:34:10 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
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for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
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explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
5edb03ee57
ARM Binary encoding information for BFC/BFI instructions.
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llvm-svn: 117072
2010-10-21 22:03:21 +00:00
2bfa8ed045
Move the encoding logic for Q registers into getMachineOpValue().
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llvm-svn: 117060
2010-10-21 20:49:13 +00:00
68a335e185
ARM mode encoding information for UBFX and SBFX instructions.
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llvm-svn: 116588
2010-10-15 17:15:16 +00:00
6f52f8a87d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
...
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
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llvm-svn: 116421
2010-10-13 19:56:10 +00:00
efd5369749
Add the rest of the ARM so_reg encoding options (register shifted register)
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and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
Duncan Sands