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20573 Commits

Author SHA1 Message Date
Devang Patel 63fe5697f4 Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] 
llvm-svn: 149142
 2012-01-27 19:48:28 +00:00
Craig Topper 5639e9e8fb Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition. 
llvm-svn: 149122
 2012-01-27 07:09:40 +00:00
Jim Grosbach 8f28dbdde5 Keep source location information for X86 MCFixup's. 
llvm-svn: 149106
 2012-01-27 00:51:27 +00:00
Jim Grosbach 20275a8577 Better user diagnostics for more ARM MachO relocation errors. 
llvm-svn: 149102
 2012-01-27 00:37:12 +00:00
Jim Grosbach b591277c4a Better diagnostic for malformed .org assembly directive. 
Provide source line number information.

llvm-svn: 149101
 2012-01-27 00:37:08 +00:00
Jim Grosbach 5e5eabb5ab Keep source information, if available, around for ARM Fixups. 
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.

Before:
LLVM ERROR: unknown ARM fixup kind!

After:
x.s:6:5: error: unsupported relocation on symbol
    beq bar
    ^

rdar://9800182

llvm-svn: 149093
 2012-01-26 23:20:15 +00:00
Jakob Stoklund Olesen fc9dce25f7 Handle call-clobbered ymm registers on Win64. 
The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.

Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered.  This allows live xmm
registers across calls.

This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.

llvm-svn: 149088
 2012-01-26 22:59:28 +00:00
Jim Grosbach c8f2b7877b Tidy up. Fix mismatched return types for error handling. 
llvm-svn: 149062
 2012-01-26 15:56:45 +00:00
James Molloy 6685c08e5f Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors. 
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.

llvm-svn: 149057
 2012-01-26 09:25:43 +00:00
Victor Umansky 5f29b0e57b Fix for the following bug in AVX codegen for double-to-int conversions: 
.	"fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
.	Currently for AVX mode for <4xdouble> and <8xdouble>  the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
.	Consequently, the conversion produces incorrect numbers.
 
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. 
As .fp_to_sint. DAG node operation is used only for lowering of  "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
 
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). 

llvm-svn: 149056
 2012-01-26 08:51:39 +00:00
Craig Topper 86e44bc829 Add HasXOP predicate check covering a bunch of XOP intrinsic patterns. 
llvm-svn: 149054
 2012-01-26 07:51:55 +00:00
Craig Topper 1c0e22f57a Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM. 
llvm-svn: 149053
 2012-01-26 07:31:30 +00:00
Craig Topper b91760eff8 Remove some more patterns by custom lowering intrinsics to target specific nodes. 
llvm-svn: 149052
 2012-01-26 07:18:03 +00:00
Anton Korobeynikov 7722a2d4e3 Properly emit ctors / dtors with priorities into desired sections 
and let linker handle the rest.

This finally fixes PR5329

llvm-svn: 148990
 2012-01-25 22:24:19 +00:00
Jim Grosbach 82f76d1275 ARM assemly parsing and validation of IT instruction. 
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

llvm-svn: 148969
 2012-01-25 19:52:01 +00:00
Chris Lattner 33633a90a0 fix a bug I introduced in r148929, this is not a splat! 
Thanks to Eli for noticing.

llvm-svn: 148947
 2012-01-25 09:56:22 +00:00
Craig Topper 7834900950 Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns. 
llvm-svn: 148933
 2012-01-25 06:43:11 +00:00
Chris Lattner 47a86bdbe2 use ConstantVector::getSplat in a few places. 
llvm-svn: 148929
 2012-01-25 06:02:56 +00:00
Craig Topper ce4f9c5668 Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary. 
llvm-svn: 148927
 2012-01-25 05:37:32 +00:00
Craig Topper 5bcf070e68 Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago. 
llvm-svn: 148922
 2012-01-25 04:42:03 +00:00
Akira Hatanaka 012f041bce Mark 64-bit register RA_64 unused too. 
llvm-svn: 148918
 2012-01-25 04:19:22 +00:00
Akira Hatanaka 01d3c42f90 Modify MipsFrameLowering::emitPrologue and emitEpilogue. 
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
  64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
  instructions which store callee-saved registers have been emitted. 
 

llvm-svn: 148917
 2012-01-25 04:12:04 +00:00
Akira Hatanaka d1d4b3efcf Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to 
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.

llvm-svn: 148916
 2012-01-25 03:55:10 +00:00
Craig Topper 3ad5bc019a Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions. 
llvm-svn: 148914
 2012-01-25 03:52:09 +00:00
NAKAMURA Takumi 6c421ea484 MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc. 
inttypes.h is not supplied in msvc.

llvm-svn: 148912
 2012-01-25 03:34:41 +00:00
NAKAMURA Takumi 96a21dcea3 Target/Mips: Unbreak CMake build. 
llvm-svn: 148909
 2012-01-25 03:15:46 +00:00
Akira Hatanaka 86d5fadd57 Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. 
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.

llvm-svn: 148908
 2012-01-25 03:01:35 +00:00
Akira Hatanaka ff36fd3de3 Add class MipsAnalyzeImmediate which comes up with an instruction sequence to 
load an immediate. 

llvm-svn: 148900
 2012-01-25 01:43:36 +00:00
Jim Grosbach 086cbfac7d NEON VLD4(all lanes) assembly parsing and encoding. 
llvm-svn: 148884
 2012-01-25 00:01:08 +00:00
Jim Grosbach ccb6d55dae Tidy up. Rename VLD4DUP patterns for consistency. 
llvm-svn: 148883
 2012-01-24 23:47:07 +00:00
Jim Grosbach b78403ce48 NEON VLD3(all lanes) assembly parsing and encoding. 
llvm-svn: 148882
 2012-01-24 23:47:04 +00:00
Akira Hatanaka d7970f9e4b Sign-extend 32-bit integer arguments when they are passed in 64-bit registers, 
which is what N32/64 does.

llvm-svn: 148875
 2012-01-24 23:18:43 +00:00
Akira Hatanaka 7e6c195c11 Pass CCState by reference. 
llvm-svn: 148871
 2012-01-24 22:07:36 +00:00
Akira Hatanaka 77dbd786c8 Pattern for f32 to i64 conversion. 
llvm-svn: 148869
 2012-01-24 22:05:25 +00:00
Devang Patel a410ed3ced Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. 
llvm-svn: 148864
 2012-01-24 21:43:36 +00:00
Akira Hatanaka 9f7ec1538f 64-bit sign extension in register instructions. 
llvm-svn: 148862
 2012-01-24 21:41:09 +00:00
Jim Grosbach 8e2722cdb0 NEON VST4(one lane) assembly parsing and encoding. 
llvm-svn: 148836
 2012-01-24 18:53:13 +00:00
Owen Anderson d845d9d9e9 Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand. 
llvm-svn: 148833
 2012-01-24 18:37:29 +00:00
Jim Grosbach 14952a0e32 NEON VLD4(one lane) assembly parsing and encoding. 
llvm-svn: 148832
 2012-01-24 18:37:25 +00:00
Jim Grosbach 3cfef8d467 NEON Two-operand assembly aliases for VSRA. 
llvm-svn: 148821
 2012-01-24 17:55:36 +00:00
Jim Grosbach 7ae12cc546 NEON Two-operand assembly aliases for VSLI. 
llvm-svn: 148819
 2012-01-24 17:49:15 +00:00
Jim Grosbach 7b6f0f67aa NEON Two-operand assembly aliases for VSRI. 
llvm-svn: 148818
 2012-01-24 17:46:58 +00:00
Jim Grosbach 681db34eae NEON add correct predicates for some asm aliases. 
llvm-svn: 148815
 2012-01-24 17:23:29 +00:00
Chris Lattner 139822fc83 C++, CBE, and TLOF support for ConstantDataSequential 
llvm-svn: 148805
 2012-01-24 14:17:05 +00:00
Elena Demikhovsky 0b0c5d8c4c ZERO_EXTEND operation is optimized for AVX. 
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.

llvm-svn: 148803
 2012-01-24 13:54:13 +00:00
Anton Korobeynikov 3cad0c21ed Use correct register class for am2offset register operands. 
This pacifies machine verifier

llvm-svn: 148782
 2012-01-24 04:58:56 +00:00
Craig Topper 0d8e67aebd Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types. 
llvm-svn: 148771
 2012-01-24 03:03:17 +00:00
Jim Grosbach da70eac268 NEON VST4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148764
 2012-01-24 00:58:13 +00:00
Jim Grosbach ed561fc850 NEON VLD4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148762
 2012-01-24 00:43:17 +00:00
Jim Grosbach 1e946a4f91 Tidy up. Remove some vertical space for readability. 
llvm-svn: 148761
 2012-01-24 00:43:12 +00:00