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998 Commits

Author SHA1 Message Date
Akira Hatanaka 012f041bce Mark 64-bit register RA_64 unused too. 
llvm-svn: 148918
 2012-01-25 04:19:22 +00:00
Akira Hatanaka 01d3c42f90 Modify MipsFrameLowering::emitPrologue and emitEpilogue. 
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
  64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
  instructions which store callee-saved registers have been emitted. 
 

llvm-svn: 148917
 2012-01-25 04:12:04 +00:00
Akira Hatanaka d1d4b3efcf Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to 
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.

llvm-svn: 148916
 2012-01-25 03:55:10 +00:00
NAKAMURA Takumi 6c421ea484 MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc. 
inttypes.h is not supplied in msvc.

llvm-svn: 148912
 2012-01-25 03:34:41 +00:00
NAKAMURA Takumi 96a21dcea3 Target/Mips: Unbreak CMake build. 
llvm-svn: 148909
 2012-01-25 03:15:46 +00:00
Akira Hatanaka 86d5fadd57 Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. 
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.

llvm-svn: 148908
 2012-01-25 03:01:35 +00:00
Akira Hatanaka ff36fd3de3 Add class MipsAnalyzeImmediate which comes up with an instruction sequence to 
load an immediate. 

llvm-svn: 148900
 2012-01-25 01:43:36 +00:00
Akira Hatanaka d7970f9e4b Sign-extend 32-bit integer arguments when they are passed in 64-bit registers, 
which is what N32/64 does.

llvm-svn: 148875
 2012-01-24 23:18:43 +00:00
Akira Hatanaka 7e6c195c11 Pass CCState by reference. 
llvm-svn: 148871
 2012-01-24 22:07:36 +00:00
Akira Hatanaka 77dbd786c8 Pattern for f32 to i64 conversion. 
llvm-svn: 148869
 2012-01-24 22:05:25 +00:00
Akira Hatanaka 9f7ec1538f 64-bit sign extension in register instructions. 
llvm-svn: 148862
 2012-01-24 21:41:09 +00:00
Owen Anderson d845d9d9e9 Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand. 
llvm-svn: 148833
 2012-01-24 18:37:29 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Jakob Stoklund Olesen f1fb1d2375 Ignore register mask operands when lowering instructions to MC. 
This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

llvm-svn: 148437
 2012-01-18 23:52:19 +00:00
Jim Grosbach aba3de99c0 Tidy up. MCAsmBackend naming conventions. 
llvm-svn: 148400
 2012-01-18 18:52:16 +00:00
Jakob Stoklund Olesen f43b599550 Add a CoveredBySubRegs property to Register descriptions. 
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363
 2012-01-18 00:16:39 +00:00
David Blaikie 486df738c3 Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly. 
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

llvm-svn: 148262
 2012-01-16 23:24:27 +00:00
Rafael Espindola 647841b181 Add big endian mips support. Based on a patch by Jack Carter. 
llvm-svn: 147924
 2012-01-11 04:04:14 +00:00
Rafael Espindola 870c4e92b9 Add the skeleton of an asm parser for mips. 
llvm-svn: 147923
 2012-01-11 03:56:41 +00:00
Benjamin Kramer 6898db6269 Remove VectorExtras. This unused helper was written for a type of API that is discouraged now. 
llvm-svn: 147738
 2012-01-07 19:42:13 +00:00
Chad Rosier a3d90a9467 Fix uninitialized variable warning. 
llvm-svn: 147676
 2012-01-06 20:02:49 +00:00
Akira Hatanaka aac3e06bf7 Enable -soft-float for MIPS. 
llvm-svn: 147541
 2012-01-04 19:29:11 +00:00
Akira Hatanaka 3b775b8cc3 Rename immLUiOpnd. 
llvm-svn: 147519
 2012-01-04 03:09:26 +00:00
Akira Hatanaka b89a4bfe41 - Define base classes for Jump-and-link instructions and make 32-bit and 64-bit 
versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.

llvm-svn: 147518
 2012-01-04 03:02:47 +00:00
Akira Hatanaka c669d7a6db Have getRegForInlineAsmConstraint return the correct register class when target 
is Mips64.

llvm-svn: 147516
 2012-01-04 02:45:01 +00:00
Bruno Cardoso Lopes cd1d447d62 Cleanup Mips code and rename some variables. Patch by Jack Carter 
llvm-svn: 147383
 2011-12-30 21:09:41 +00:00
Bruno Cardoso Lopes d5b2834fb7 Improve Mips JIT. 
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.

Patch by Sasa Stankovic

llvm-svn: 147382
 2011-12-30 21:04:30 +00:00
Akira Hatanaka 1cf7576707 Add MachineMemOperands to instructions generated in storeRegToStackSlot or 
loadRegFromStackSlot. 

llvm-svn: 147235
 2011-12-24 03:11:18 +00:00
Akira Hatanaka 6f54a46133 Detect unaligned loads/stores that have been added for Mips64 support. 
llvm-svn: 147234
 2011-12-24 03:07:37 +00:00
Akira Hatanaka 695d113adc If target ABI is N64, LEA should be daddiu. 
llvm-svn: 147232
 2011-12-24 02:59:27 +00:00
Rafael Espindola 1dc45d8df4 Move the Mips only bits of the ELF writer to lib/Target/Mips. 
llvm-svn: 147133
 2011-12-22 03:03:17 +00:00
Akira Hatanaka e2eed9649e Local dynamic TLS model for direct object output. Create the correct TLS MIPS 
ELF relocations.

Patch by Jack Carter.

llvm-svn: 147118
 2011-12-22 01:05:17 +00:00
Rafael Espindola 1ad4095d6b Reduce the exposure of Triple::OSType in the ELF object writer. This will 
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

llvm-svn: 147059
 2011-12-21 17:00:36 +00:00
Akira Hatanaka 964c891e61 Fix bug in zero-store peephole pattern reported in pr11615. 
The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024
 2011-12-21 00:31:10 +00:00
Akira Hatanaka 1d8efaba7e Expand 64-bit CTLZ nodes if target architecture does not support it. Add test 
case for DCLO and DCLZ.

llvm-svn: 147022
 2011-12-21 00:20:27 +00:00
Akira Hatanaka 410ce9cb44 Expand 64-bit CTPOP and CTTZ. 
llvm-svn: 147021
 2011-12-21 00:14:05 +00:00
Akira Hatanaka 91c052c4d8 Expand 64-bit atomic load and store. 
llvm-svn: 147019
 2011-12-21 00:02:58 +00:00
Akira Hatanaka 4706ac9715 Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017
 2011-12-20 23:56:43 +00:00
Akira Hatanaka 43c1ff4db3 Add definition of WSBH (Word Swap Bytes within Halfwords), which is an 
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015
 2011-12-20 23:47:44 +00:00
Akira Hatanaka 79aed157e7 64-bit uint-fp conversion nodes are expanded. 
llvm-svn: 147014
 2011-12-20 23:40:56 +00:00
Akira Hatanaka 2bb8d068f5 Enable custom lowering DYNAMIC_STACKALLOC nodes. 
llvm-svn: 147013
 2011-12-20 23:35:46 +00:00
Akira Hatanaka 8e2c02e2d6 Set the correct stack pointer register that should be saved or restored. 
llvm-svn: 147012
 2011-12-20 23:28:36 +00:00
Akira Hatanaka cb2a85bc22 Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates 
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008
 2011-12-20 23:10:57 +00:00
Akira Hatanaka 2c8d1734f8 Fix indentation. 
llvm-svn: 147007
 2011-12-20 22:58:01 +00:00
Akira Hatanaka cf10f08825 64-bit data directive. 
llvm-svn: 147005
 2011-12-20 22:52:19 +00:00
Akira Hatanaka 494fdf1499 32-to-64-bit sext_inreg pattern. 
llvm-svn: 147004
 2011-12-20 22:40:40 +00:00
Akira Hatanaka 8756816e6f Add 64-bit extload patterns. 
llvm-svn: 147003
 2011-12-20 22:36:08 +00:00
Akira Hatanaka 0cee2045c9 Add patterns for matching extloads with 64-bit address. The patterns are enabled 
only when the target ABI is N64.

llvm-svn: 147001
 2011-12-20 22:33:53 +00:00
Akira Hatanaka dac1d48d8d Add code in MipsDAGToDAGISel for selecting constant +0.0. 
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 

llvm-svn: 146999
 2011-12-20 22:25:50 +00:00
Akira Hatanaka 14468c6cb6 Revert part of r146995 that was accidentally commmitted. 
llvm-svn: 146996
 2011-12-20 22:09:36 +00:00