ee1e71e576
[X86] Use extract_vector_elt instead of X86ISD::VEXTRACT for isel of vXi1 extractions.
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llvm-svn: 320937
2017-12-17 01:35:48 +00:00
c0c2d19e08
[X86] Canonicalize extract_vector_elt from vXi1 to always return MVT::i32.
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This allows us to remove some isel patterns that allowed MVT::i8 result type.
llvm-svn: 320936
2017-12-17 01:35:47 +00:00
c08960597c
[X86] Add 128 and 256-bit VPOPCNTDQ instructions. Adjust some tablegen classes LZCNT/POPCNT.
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I think when this instruction was first published it was only for a Knights CPU and thus VLX version was missing.
llvm-svn: 320910
2017-12-16 02:40:28 +00:00
ad9221d684
[X86] Widen (v2i32 (fp_to_uint v2f64)) to (v8i32 (fp_to_uint v8f64)) during legalization if we have AVX512F, but not VLX. NFC
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Previously we widened it using isel patterns.
llvm-svn: 320824
2017-12-15 16:22:20 +00:00
468a813315
[X86] Use Ld scheduler classes for instructions with folded loads.
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llvm-svn: 320459
2017-12-12 07:06:35 +00:00
a0be5a06c1
[X86] Rename some instructions that start with Int_ to have the _Int at the end.
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This matches AVX512 version and is more consistent overall. And improves our scheduler models.
In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses.
llvm-svn: 320325
2017-12-10 19:47:56 +00:00
1de942b2d1
[X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix. Fix the scheduling information for some of them.
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Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)'
llvm-svn: 320320
2017-12-10 17:42:44 +00:00
aa904d5ab6
[X86] Fix a few instructions that were named Z512 instead of just Z.
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This makes things consistent with our normal instruction naming.
llvm-svn: 320316
2017-12-10 17:42:39 +00:00
c89e282f7d
[X86] Rename some instructions so that 'b' is added as a suffix instead of replacing an 'r'
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llvm-svn: 320290
2017-12-10 09:14:38 +00:00
da7e78e18c
[X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since they can only be selected by intrinsics.
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llvm-svn: 320283
2017-12-10 04:07:28 +00:00
a2f5528084
[X86] Remove ReadAfterLd from several several rb instructions
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This affects CVTSD2SS, FMA, RCP28, RSQRT28, and SQRT scalar instructions
'b' here refers to 'sae' not broadcast. These aren't memory instructions.
llvm-svn: 320281
2017-12-10 03:16:36 +00:00
d3e21c6b79
[X86][AVX512] Drop a default NoItinerary argument that isn't used any more. NFCI.
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Requires re-ordering of AVX512_maskable_custom arguments.
llvm-svn: 320255
2017-12-09 16:20:54 +00:00
26f106fda4
[X86][AVX512] Tag AVX512_512_SEXT_MASK_* instructions scheduler classes
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Match VPTERNLOG which these pseudos will eventually alias to
llvm-svn: 320154
2017-12-08 15:17:32 +00:00
9afbe77a91
[X86][AVX512] Tag mask reg op instruction scheduler classes
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llvm-svn: 319945
2017-12-06 19:36:00 +00:00
d255a6201d
[X86][AVX512] Tag scalar insert/extract instruction scheduler classes
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Classes don't look great but match what we're doing on SSE/AVX
llvm-svn: 319920
2017-12-06 18:46:06 +00:00
df05251921
[X86][AVX512] Tag aligned/unaligned move instruction scheduler classes
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llvm-svn: 319913
2017-12-06 17:59:26 +00:00
aa902be158
[X86][AVX512] Tag BROADCAST instruction scheduler classes
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llvm-svn: 319900
2017-12-06 15:48:40 +00:00
07dc6d6975
[X86][AVX512] Drop default NoItinerary arguments that aren't needed
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Requires reordering of AVX512_maskable_common arguments, but helps track what is still missing itinerary tags
llvm-svn: 319890
2017-12-06 13:14:44 +00:00
bfe969c49b
[X86][AVX512] Tag Mask<->Vector instructions scheduler classes
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llvm-svn: 319887
2017-12-06 11:59:05 +00:00
75673946fc
[X86][AVX512] Cleanup scalar move scheduler classes
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llvm-svn: 319884
2017-12-06 11:23:13 +00:00
d495301414
[X86][AVX512] Tag BLENDM instruction scheduler classes
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llvm-svn: 319833
2017-12-05 21:05:25 +00:00
b69dae42e3
[X86][AVX512] Tag GATHER/SCATTER instruction scheduler classes
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NOTE: At the moment these use the WriteLoad/WriteStore classes, which severely underestimates the costs. This needs to be reviewed.
llvm-svn: 319829
2017-12-05 20:47:11 +00:00
13d449d3e2
[X86][AVX512] Tag VPSLLDQ/VPSRLDQ instruction scheduler classes
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llvm-svn: 319822
2017-12-05 20:16:22 +00:00
833c260a4b
[X86][AVX512] Tag VPTRUNC/VPMOVSX/VPMOVZX instruction scheduler classes
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llvm-svn: 319815
2017-12-05 19:21:28 +00:00
d9f1ae3266
[X86][AVX512] Tag VNNIW instruction scheduler classes
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llvm-svn: 319784
2017-12-05 16:17:21 +00:00
4a9b1e1273
[X86][AVX512] Drop some default NoItinerary arguments that aren't needed any more
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llvm-svn: 319782
2017-12-05 16:10:57 +00:00
4d08aedba3
[X86][AVX512] Tag VPMADD52/VPSADBW instruction scheduler classes
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llvm-svn: 319772
2017-12-05 14:59:40 +00:00
71660c61e6
[X86][AVX512] Add missing scalar CMPSS/CMPSD logic scheduler classes
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llvm-svn: 319770
2017-12-05 14:34:42 +00:00
b9b46394e3
[X86][AVX512] Cleanup bit logic scheduler classes
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llvm-svn: 319767
2017-12-05 14:04:23 +00:00
fd3a2632e5
[X86][AVX512] Tag scalar CVT and CMP instruction scheduler classes
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llvm-svn: 319765
2017-12-05 13:49:44 +00:00
aa91155960
[X86][AVX512] Tag VPCMP/VPCMPU instruction scheduler classes
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Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now.
llvm-svn: 319760
2017-12-05 12:14:36 +00:00
a2b5862641
[X86][AVX512] Cleanup VPCMP scheduler classes
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Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now.
llvm-svn: 319758
2017-12-05 12:02:22 +00:00
54b8aa2bb2
[X86][AVX512] Tag VFIXUPIMM instructions scheduler classes
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llvm-svn: 319757
2017-12-05 11:46:57 +00:00
4520d4f8ad
[X86] Allow VPMAXUQ/VPMAXSQ/VPMINUQ/VPMINSQ to be used with 128/256 bit vectors when AVX512 is enabled.
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These instructions can be used by widening to 512-bits and extracting back to 128/256. We do similar to several other instructions already.
llvm-svn: 319641
2017-12-04 07:21:01 +00:00
569e53b0f6
[X86][AVX512] Tag PH2PS/PS2PH conversion instructions scheduler classes
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llvm-svn: 319637
2017-12-03 21:43:54 +00:00
465a88bb92
[X86][AVX512] Tag packed F2I/I2F/F2F conversion instructions scheduler class
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llvm-svn: 319636
2017-12-03 21:16:12 +00:00
031d8b71b3
[X86][AVX512] Tag subvector extract/insert instructions scheduler classes
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llvm-svn: 319568
2017-12-01 18:40:32 +00:00
8d5e469c32
Fix line endings. NFCI.
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llvm-svn: 319559
2017-12-01 17:24:15 +00:00
fb01cb1b0c
[X86][AVX512] Tag VPERM2I/VPERM2T instructions scheduler class
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llvm-svn: 319558
2017-12-01 17:23:06 +00:00
54c6083fb1
[X86][AVX512] Tag VFPCLASS instructions scheduler class
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llvm-svn: 319554
2017-12-01 16:51:48 +00:00
07b4c5917e
[X86][AVX512] Tag VPSHUFBITQMB instructions scheduler class
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llvm-svn: 319553
2017-12-01 16:35:57 +00:00
904d1a895c
[X86][AVX512] Tag VPCOMRESS/VPEXPAND instructions scheduler classes
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llvm-svn: 319551
2017-12-01 16:20:03 +00:00
2dc4ff1cde
[X86][AVX512] Tag vshift/vpermv/pshufd/pshufb instructions scheduler classes
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llvm-svn: 319540
2017-12-01 13:25:54 +00:00
bb791b3dbd
[X86][AVX512] Tag fcmp/ptest/ternlog instructions scheduler classes
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llvm-svn: 319433
2017-11-30 13:18:06 +00:00
d1a7d0c3f1
[X86][AVX512] Tag binop/rounding/sae instructions scheduler classes
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llvm-svn: 319424
2017-11-30 12:01:52 +00:00
3e5987cf8d
[X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes
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llvm-svn: 319418
2017-11-30 10:48:47 +00:00
4d2c703492
[X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes (REVERSION)
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Accidental commit of incomplete patch
llvm-svn: 319346
2017-11-29 19:37:38 +00:00
87034cb498
[X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes
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llvm-svn: 319338
2017-11-29 19:19:59 +00:00
36be852cee
[X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions scheduler classes
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llvm-svn: 319337
2017-11-29 18:52:20 +00:00
6a00970ade
[X86][AVX512] Add itinerary argument to all AVX512_maskable_* wrappers. NFCI
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All default to NoItinerary
llvm-svn: 319326
2017-11-29 17:21:15 +00:00
Craig Topper