0ad4c265d7
[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero
...
c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C.
This patch adds uimmlog2xlennonzero to reflect this constraint as well as
tests.
Differential Revision: https://reviews.llvm.org/D41216
Patch by Shiva Chen.
llvm-svn: 320799
2017-12-15 10:20:51 +00:00
60714f98ba
[RISCV] MC layer support for the remaining RVC instructions
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Differential Revision: https://reviews.llvm.org/D40003
Patch by Shiva Chen.
llvm-svn: 320558
2017-12-13 09:32:55 +00:00
f8f4b90544
[RISCV] MC layer support for the jump/branch instructions of the RVC extension
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Differential Revision: https://reviews.llvm.org/D40002
Patch by Shiva Chen.
llvm-svn: 320038
2017-12-07 13:19:57 +00:00
9f6aec4b7a
[RISCV] MC layer support for load/store instructions of the C (compressed) extension
...
Differential Revision: https://reviews.llvm.org/D40001
Patch by Shiva Chen.
llvm-svn: 320037
2017-12-07 12:50:32 +00:00
Alex Bradbury