9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
...
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
3f9c17906f
Disable switch lowering for targets based on the selection dag isel,
...
letting the code generator handle them directly.
llvm-svn: 27539
2006-04-08 19:46:55 +00:00
2d7298c362
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
d1aa1638c6
Expose base register for DwarfWriter. Refactor code accordingly.
...
llvm-svn: 27225
2006-03-28 13:48:33 +00:00
fa53b276d0
Translate llvm target registers to dwarf register numbers properly.
...
llvm-svn: 27180
2006-03-27 20:18:45 +00:00
5d70a7c4a5
#include Intrinsics.h into all dag isels
...
llvm-svn: 27109
2006-03-25 06:47:10 +00:00
f0729b4067
Add dwarf register numbering to register data.
...
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
3c43609f1f
Add support to locate local variables in frames (early version.)
...
llvm-svn: 26994
2006-03-23 18:12:57 +00:00
6f95ab7abb
Eliminate IntrinsicLowering from TargetMachine.
...
Make the CBE and V9 backends create their own, since they're the only ones that use it.
llvm-svn: 26974
2006-03-23 05:43:16 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
2dd2c652b2
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
...
llvm-svn: 26742
2006-03-13 23:20:37 +00:00
e363fdf318
Add support for 'special' llvm globals like debug info and static ctors/dtors.
...
llvm-svn: 26628
2006-03-09 06:14:35 +00:00
5005b01c20
doo de doo
...
llvm-svn: 26614
2006-03-08 06:18:46 +00:00
9c7f50376a
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
...
implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
36a2ee299e
distinguish between objects and register names, now we can have stuff
...
with names like "f84", "in6" etc etc.
this should fix one or two tests
llvm-svn: 26232
2006-02-16 13:12:57 +00:00
62c3484e43
Switch targets over to using SelectionDAG::getCALLSEQ_START to create
...
CALLSEQ_START nodes.
llvm-svn: 26143
2006-02-13 09:00:43 +00:00
4698e4f5fe
fix storing booleans (grawp missed this one)
...
llvm-svn: 26120
2006-02-11 07:33:17 +00:00
0010a92375
now short immediates will get matched (previously constants were all
...
triggering movl 64bit imm fat instructions)
llvm-svn: 26119
2006-02-11 07:32:15 +00:00
d1b82d8db0
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
...
llvm-svn: 26085
2006-02-09 07:17:49 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
54cb1833a4
Use SelectRoot() as entry of any tblgen based isel.
...
llvm-svn: 25997
2006-02-05 06:46:41 +00:00
7e7f439f85
Fix some of the stuff in the PPC README file, and clean up legalization
...
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
llvm-svn: 25875
2006-02-01 07:19:44 +00:00
32be2dc0af
Allow the specification of explicit alignments for constant pool entries.
...
llvm-svn: 25855
2006-01-31 22:23:14 +00:00
61c9a8e942
Targets all now request ConstantFP to be legalized into TargetConstantFP.
...
'fpimm' in .td files is now TargetConstantFP.
llvm-svn: 25771
2006-01-29 06:26:08 +00:00
595ec734fc
Implement Promote for VAARG, and allow it to be custom promoted for people
...
who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
b292de6703
Remove some dead code
...
llvm-svn: 25719
2006-01-28 00:02:51 +00:00
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
...
llvm-svn: 25674
2006-01-27 01:46:15 +00:00
0ebb0b1c5c
fix stack corruption! Previously, 16-byte whole-FP-register stores were
...
being treated as needing only 8 bytes (though they were 16 byte aligned.)
This should fix a bunch of tests - anyone have any comments, though?
- in Target.td , SpillSize and SpillAlignment seem dead - is this what
Size and Alignment do now?
- in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
DeclaredSpillAlignment seem dead.
- there are a bunch of comments here and there that don't clearly
distinguish between 'size' and 'spillsize' etc. hmm.
llvm-svn: 25644
2006-01-26 09:45:03 +00:00
c090ac13bd
some hoovering
...
llvm-svn: 25643
2006-01-26 09:08:31 +00:00
030e002fb9
Set SchedulingForLatency to be the default scheduling preference for all.
...
llvm-svn: 25607
2006-01-25 18:52:42 +00:00
e74795cd70
First part of bug 680:
...
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
1092a02619
Default scheduling preference is SchedulingForLatency.
...
llvm-svn: 25603
2006-01-25 09:15:54 +00:00
5ea06a9f13
add bundling! well not really, for now it's just stop-insertion.
...
llvm-svn: 25593
2006-01-25 02:23:38 +00:00
37c8ad14f4
die, die!! r15, you are not callee-saved
...
llvm-svn: 25527
2006-01-23 06:11:45 +00:00
cc87402925
fix register corruption! (my god.) r15 is a scratch reg, using that as
...
a frame pointer is a pretty doofus thing to do. use r5 instead, and
mark it callee-saved, coz that's what it is!
llvm-svn: 25526
2006-01-23 06:08:46 +00:00
de02d7727f
Add explicit #includes of <iostream>
...
llvm-svn: 25515
2006-01-22 23:41:00 +00:00
4204e02fc6
insignificant, but next up is proper stack frame layout!
...
llvm-svn: 25497
2006-01-21 14:27:19 +00:00
f54c9395e7
remove RET hack, add proper support for rets (watching out for ret voids)
...
llvm-svn: 25486
2006-01-20 20:24:31 +00:00
4026e12e85
fix sext breakage: now we correctly deal with functions that return
...
int vs uint
llvm-svn: 25478
2006-01-20 16:10:05 +00:00
9a8fb20689
fix storing bools! eek!
...
llvm-svn: 25476
2006-01-20 03:40:25 +00:00
550d8ec1ad
fix boolean XOR (which fixes up comparisons..)
...
llvm-svn: 25462
2006-01-19 15:18:56 +00:00
4d69a01254
BOOM!
...
llvm-svn: 25460
2006-01-19 14:14:11 +00:00
bcbcfac6ea
click click
...
llvm-svn: 25459
2006-01-19 14:13:11 +00:00
29b9d7cdff
fix calls that return f32
...
llvm-svn: 25455
2006-01-19 08:31:51 +00:00
e08a95d3c1
oops, this shouldn't have gotten in
...
llvm-svn: 25388
2006-01-17 03:09:48 +00:00
266ff6056a
use proper (82-bit) spills/fills when spilling FP regs, so that
...
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)
llvm-svn: 25385
2006-01-17 02:04:52 +00:00
c261469ad9
fixing divides
...
llvm-svn: 25383
2006-01-17 01:19:49 +00:00
e995910e64
fixing divides: FP should now be 100%, and integers are fine too
...
unless you try to div/mod 0 by anything, in which case you will
get some cute number, and not 0, which is bad.
llvm-svn: 25358
2006-01-16 14:33:04 +00:00
ba187774fe
fix division! again!! pattern isel, prepare to die.
...
llvm-svn: 25353
2006-01-16 06:33:38 +00:00
c8817d2857
explain that r12 is the stack pointer reg
...
llvm-svn: 25336
2006-01-15 09:45:23 +00:00
c17b41c3ba
Cleanup IA64ISD, tell the graph drawer what the symbolic names for the enums are.
...
llvm-svn: 25324
2006-01-14 22:27:21 +00:00
2fba8a3aaa
bswap implementation
...
llvm-svn: 25312
2006-01-14 03:14:10 +00:00
0b94324c5e
don't be a doofus - this fixes storing bools
...
llvm-svn: 25274
2006-01-13 10:28:25 +00:00
fdc6d1ea69
new nodes
...
llvm-svn: 25271
2006-01-13 02:40:58 +00:00
84be729a56
sabre's (correct) fix means these guys need to be flagged as well (else
...
the scheduler will complain)
llvm-svn: 25241
2006-01-12 03:28:40 +00:00
9d5e4e8f3c
Fix an itanium call lowering bug for duraid
...
llvm-svn: 25235
2006-01-12 01:33:08 +00:00
6b9e00dedc
Missed a spot.
...
llvm-svn: 25233
2006-01-11 23:20:28 +00:00
1b8121b227
Add bswap, rotl, and rotr nodes
...
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
llvm-svn: 25222
2006-01-11 21:21:00 +00:00
eaf94a8d2e
tblgen does this now
...
llvm-svn: 25220
2006-01-11 19:53:22 +00:00
0302e62296
cleanup GETFD
...
llvm-svn: 25198
2006-01-11 03:50:40 +00:00
c712fd6b4e
this just might work
...
llvm-svn: 25195
2006-01-11 01:38:07 +00:00
0d5d08b26e
add support for selecting bools
...
FIXME: this is commented out because it makes tblgen go a bit fruity
llvm-svn: 25193
2006-01-11 01:21:12 +00:00
0fb2ae7d17
silence a bogus warning
...
llvm-svn: 25185
2006-01-10 19:45:18 +00:00
014e8ee806
heh, 'sif it'd be a legalizer bug.
...
llvm-svn: 25172
2006-01-10 05:26:01 +00:00
e977a93bd5
support functions that return bool (this "should" work but doesn't,
...
*maybe* due to a legalizer bug.)
llvm-svn: 25171
2006-01-10 05:08:25 +00:00
efbb8da3f5
silence a bogus gcc warning
...
llvm-svn: 25129
2006-01-06 17:56:38 +00:00
deeafa0f00
Had expand logic backward.
...
llvm-svn: 25105
2006-01-05 01:47:43 +00:00
762e9ec06c
Added initial support for DEBUG_LABEL allowing debug specific labels to be
...
inserted in the code.
llvm-svn: 25104
2006-01-05 01:25:28 +00:00
69ac08c683
nasty paste-o, calls passing more than 8 arguments along were having
...
args >8 put into the wrong place
llvm-svn: 25027
2005-12-27 10:17:03 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
6b240e55d1
unbreak calls, a few more tests should run. Tomorrow: bugpoint!
...
llvm-svn: 25010
2005-12-25 14:09:08 +00:00
06dcc199f0
we don't feed our call instructions extra operands
...
llvm-svn: 25009
2005-12-25 14:07:01 +00:00
177d7af5d5
remove dead code
...
llvm-svn: 24965
2005-12-22 21:16:08 +00:00
644e7db818
this is a hack, which may or may not hang around. In short:
...
whimper out of doing things the Right Way, and hack up a generic
'BRCALL' instruction, that gets generated when calls are lowered.
This gets selected by hand in the DAG isel, where it gets turned
into real (i.e. in tablegen) br.call instructions.
BUG: this dies on void calls, but seems to work otherwise?
llvm-svn: 24952
2005-12-22 13:29:14 +00:00
3692fa14b8
we can't do this directly in lowering, so we need this case
...
llvm-svn: 24951
2005-12-22 07:14:45 +00:00
3608ab87c0
oops, back this out
...
llvm-svn: 24950
2005-12-22 07:13:51 +00:00
b1d57fb175
we can't all have brains now, can we
...
llvm-svn: 24948
2005-12-22 06:41:39 +00:00
d0c146d59f
this should take care of calls to varadic functions, but it doesn.,t
...
BUG: calling printf(string, float) will load the float into the wrong
register, completely forget about loading the string, etce
llvm-svn: 24947
2005-12-22 06:39:57 +00:00
a8de8a5db4
we need to emit the getf.d instruction in lowering, so add it
...
to IA64ISD
llvm-svn: 24946
2005-12-22 06:38:38 +00:00
5ccf76fed3
I shoulda done this a *long* time ago (tm): implement calls properly,
...
i.e. r1/r12/rp are saved/restored regardless of scheduling/luck
TODO: calls to external symbols, indirect (function descriptor) calls,
performance (we're being paranoid right now)
BUG: the code for handling calls to vararg functions breaks if FP
args are passed (this will make printf() go haywire so a bunch of
tests will fail)
BUG: this seems to trigger some legalize nastiness
llvm-svn: 24942
2005-12-22 04:07:40 +00:00
8f6c86fe3b
kill SelectCALL() in the DAG isel, we handle this in lowering now, like
...
SPARCv8. (we copy sparcv8's workaround for tablegen not being nice about
ISD::CALL/TAILCALL)
llvm-svn: 24941
2005-12-22 03:58:17 +00:00
a743e00e7a
update tablegen files - nothing to see here
...
llvm-svn: 24939
2005-12-22 03:56:03 +00:00
9e296bee9a
Disengage DEBUG_LOC from non-PPC targets.
...
llvm-svn: 24919
2005-12-21 20:51:37 +00:00
c54cddd25b
Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.
...
llvm-svn: 24595
2005-12-05 02:34:29 +00:00
93feffb4ed
IA64 doesn't support the LOCATION node, and for some reason the ISelPattern
...
stuff isn't using ISelLowering.cpp
llvm-svn: 24567
2005-12-01 18:19:53 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
...
work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
a75694aa16
Pay attn to the node returned by SelectNodeTo
...
llvm-svn: 24551
2005-11-30 23:02:08 +00:00
6f8c1ace6e
No longer track value types for asm printer operands, and remove them as
...
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
llvm-svn: 24541
2005-11-30 18:54:35 +00:00
9c415364cf
No targets support line number info yet.
...
llvm-svn: 24513
2005-11-29 06:16:21 +00:00
0c88f150c6
add support for dynamic_stackalloc to the dag isel (thanks andrew ;)
...
next up: support argument passing in memory, not just registers
llvm-svn: 24490
2005-11-25 07:49:25 +00:00
8edbf805d7
add support for div/rem to the dag->dag isel. yay.
...
llvm-svn: 24472
2005-11-21 14:14:54 +00:00
b9db67a045
Eliminate unneeded intermediate class. Move doFinalizeMethod to bottom of
...
file.
llvm-svn: 24470
2005-11-21 08:40:17 +00:00
b55de47595
Start using shared asmprinter Constant Pool emitter, use shorter cpi names.
...
llvm-svn: 24469
2005-11-21 08:38:26 +00:00
99946fb63f
Adjust to capitalized AsmPrinter method names
...
llvm-svn: 24456
2005-11-21 07:51:23 +00:00
2b53ea99b0
Use PrivateGlobalPrefix for basic block labels
...
llvm-svn: 24452
2005-11-21 07:39:22 +00:00
2bccd73dbb
Start using SwitchSection, allowing globals and functions to be emitted
...
to specific sections. Delete some dead functions copied from the X86 backend.
llvm-svn: 24449
2005-11-21 07:26:04 +00:00
2c0b435ba6
Rename SwitchSection -> switchSection to avoid conflicting with a future
...
change.
llvm-svn: 24443
2005-11-21 06:55:27 +00:00
8a4995e42a
Start using PrivateGlobalPrefix correctly
...
llvm-svn: 24442
2005-11-21 06:51:52 +00:00
76034f95f6
add FP select. next up - divide!
...
llvm-svn: 24346
2005-11-14 01:17:30 +00:00
b28f214033
Add a new option to indicate we want the code generator to emit code quickly,not spending tons of time microoptimizing it. This is useful for an -O0style of build.
...
llvm-svn: 24233
2005-11-08 02:11:51 +00:00
3c1c8c55c3
add support for storing and returning bools
...
llvm-svn: 24228
2005-11-07 03:11:02 +00:00
4a30d4a460
just some random hacking - calls (particularly indirect) need a lot of
...
love (especially with -sched=simple)
llvm-svn: 24225
2005-11-06 13:43:30 +00:00
4645db0948
ask for 16-byte aligned jmpbufs. This should unbreak C++ on IA64 (and
...
a bunch of other things) but is currently ignored by the code
generator.
llvm-svn: 24206
2005-11-06 04:29:30 +00:00
31071b7471
oops, forgot to load GP for indirect calls, though the old code now commented
...
out failed (e.g. methcall) - now the code compiles, though it's not quite
right just yet (tm) ;)
would fix this but it's 3am! :O
llvm-svn: 24186
2005-11-04 17:55:53 +00:00
d3260128af
kill redundant SP/GP/RP save/restores across calls
...
llvm-svn: 24183
2005-11-04 10:01:10 +00:00
fc1d1b2499
add support for loading bools
...
llvm-svn: 24182
2005-11-04 09:59:06 +00:00
7ac646ef95
fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1)
...
llvm-svn: 24175
2005-11-04 00:57:56 +00:00
f0f22a55b0
add pattern to load constant 0 into a predicate reg
...
llvm-svn: 24164
2005-11-03 10:09:32 +00:00
674660ff03
Fix a bug that prevented this pattern from matching
...
llvm-svn: 24161
2005-11-03 05:45:34 +00:00
955ffafd79
"fix" support for FP constants (this code asserts in the scheduler,
...
though)
llvm-svn: 24152
2005-11-02 07:32:59 +00:00
4480dcdcea
add F0 and F1 to the FP register class
...
llvm-svn: 24151
2005-11-02 07:30:39 +00:00
b5310bdbe9
This works now
...
llvm-svn: 24150
2005-11-02 06:49:37 +00:00
17decbb253
add support for SELECT to TargetSelectionDAG.td, add support for
...
selecting ints to IA64, and a few other ia64 bits and pieces
llvm-svn: 24147
2005-11-02 02:37:18 +00:00
9abf1650ed
add support for loading FP constants +0.0 and +1.0 to the dag isel,
...
stop pretending -0.0 and -1.0 are machine constants
llvm-svn: 24146
2005-11-02 02:35:04 +00:00
5a087ff8c3
heh, scheduling was easy?
...
need to send chris, jim and sampo a box of fish each
llvm-svn: 24135
2005-11-01 05:49:08 +00:00
9b61d3c1e2
FORTRAN!!! :( and other similarly unfortunate things mean that on ia64
...
one sometimes needs to pass FP args in both FP *and* integer registers.
llvm-svn: 24134
2005-11-01 05:46:16 +00:00
b81b61330e
so tablegen was thinking I might want to convert FPs to predicates.
...
clever little tablegen!
llvm-svn: 24133
2005-11-01 03:32:15 +00:00
6c912bffd6
add support for int->FP and FP->int ops, and add ia64 patterns for these
...
llvm-svn: 24132
2005-11-01 03:07:25 +00:00
a284b6636f
add zeroextend predicate->integer
...
llvm-svn: 24131
2005-11-01 01:29:55 +00:00
88fc69f627
add FP compares and implicit register defs to the dag isel
...
llvm-svn: 24118
2005-10-31 01:42:11 +00:00
57b7ee9da8
fix some broken comparisons, this affected the Pattern isel too.
...
llvm-svn: 24109
2005-10-30 10:14:19 +00:00
7abaf906e2
add some FP stuff, some mix.* stuff, and constant pool support to the
...
DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream
llvm-svn: 24094
2005-10-29 16:08:30 +00:00
c252f33fdb
add shladd
...
llvm-svn: 24080
2005-10-29 04:13:40 +00:00
12fca42062
These are autogenerated
...
llvm-svn: 24063
2005-10-28 18:26:52 +00:00
f221c261f3
DAG->DAG instruction selection for ia64! "hello world" works, not much else.
...
use -enable-ia64-dag-isel to turn this on
TODO: delete lowering stuff from the pattern isel
: get operations on predicate bits working
: get other bits of pseudocode going
: use sampo's mulh/mull-using divide-by-constant magic
: *so* many patterns ("extr", "tbit" and "dep" will be fun :)
: add FP
: add a JIT!
: get it working 100%
in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.
OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.
llvm-svn: 24058
2005-10-28 17:46:35 +00:00
529169cab2
remove dead stuff
...
llvm-svn: 24054
2005-10-28 04:58:24 +00:00
e68a807025
Eliminate getClass, it is not needed
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llvm-svn: 24053
2005-10-28 04:57:11 +00:00
ae5d9bd65b
Don't generate operations that aren't yet supported
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llvm-svn: 23858
2005-10-21 01:52:45 +00:00
cd8b421799
Fix CodeGen/Generic/bool-to-double.ll
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llvm-svn: 23652
2005-10-07 04:50:48 +00:00
6169a78f46
these registers don't belong to any register classes, so don't mark them
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as callee save. They can never be generated by the compiler.
llvm-svn: 23551
2005-09-30 06:42:24 +00:00
64ca7cda3f
these methods get extra args
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llvm-svn: 23538
2005-09-30 01:30:55 +00:00
0815dcae3f
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
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Though I have done extensive testing, it is possible that this will break
things in configs I can't test. Please let me know if this causes a problem
and I'll fix it ASAP.
llvm-svn: 23505
2005-09-28 22:29:17 +00:00
9e4a4ee3dc
Give all operands names
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llvm-svn: 23357
2005-09-14 21:11:13 +00:00
7c8dba750c
ignore generated files
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llvm-svn: 23263
2005-09-07 23:47:44 +00:00
2493f0e5fd
Handle ANY_EXTEND like ZERO_EXTEND. Simplify the extend/truncate code on
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the observation that it only has to handle i1 -> i64 and i64 -> i1.
llvm-svn: 23201
2005-09-02 00:15:30 +00:00
19058c3989
1. Use SubtargetFeatures in llc/lli.
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2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
llvm-svn: 23192
2005-09-01 21:38:21 +00:00
d0dc6f4299
Fix a bug in my previous checkin
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llvm-svn: 23082
2005-08-26 17:18:44 +00:00
c30405e0ee
Change ConstantPoolSDNode to actually hold the Constant itself instead of
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putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
llvm-svn: 23081
2005-08-26 17:15:30 +00:00
daae1e10f7
fix a warning in optimized build
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llvm-svn: 23030
2005-08-25 00:03:21 +00:00
d2f2aff484
Fix a crash I introduced into the IA64 backend with my copyfromreg change.
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It used to crash on any function that took float arguments.
llvm-svn: 22973
2005-08-22 21:33:11 +00:00
9d46518e5c
Add a pass name for -time-passes output
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llvm-svn: 22970
2005-08-22 18:28:09 +00:00
3588ea9bf5
reenable collapse of loadimm+AND -> dep.z (thanks guys)
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llvm-svn: 22944
2005-08-21 15:43:53 +00:00
9b0a275f04
Repair an out by one error for IA64.
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llvm-svn: 22942
2005-08-20 11:05:23 +00:00
bd26a82051
Split RegisterClass 'Methods' into MethodProtos and MethodBodies
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llvm-svn: 22929
2005-08-19 19:13:20 +00:00
8975de187f
Put register classes in namespaces
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llvm-svn: 22924
2005-08-19 18:50:46 +00:00
f391f286d7
This code has always been dead on itanium
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llvm-svn: 22916
2005-08-19 18:34:37 +00:00
fcbb38077b
a bugfix (up top) and a quick repair job: disable generation of dep.z
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(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.
llvm-svn: 22904
2005-08-19 13:25:50 +00:00
3e0335c9d1
Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR.
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I'm not convinced this is all of them, but I can't do much testing, because
IA64 LLC crashes on big programs :(
llvm-svn: 22892
2005-08-19 00:47:42 +00:00
7c76278242
update the backends to work with the new CopyFromReg/CopyToReg/ImplicitDef nodes
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llvm-svn: 22807
2005-08-16 21:56:37 +00:00
371e49515d
Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty
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fixme from the PowerPC backend. Emit slightly better code for legalizing
select_cc.
llvm-svn: 22805
2005-08-16 19:49:35 +00:00
1c2f9fdf71
sorry!! this is temporary; for some reason the nasty constmul code seems to
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be an infinite loop when using g++-4.0.1*, this kills the ia64 nightly
tester. A proper fix shall be forthcoming!!! thanks for not killing me. :)
llvm-svn: 22748
2005-08-10 12:38:57 +00:00
6ec7745e80
Update the targets to the new SETCC/CondCodeSDNode interfaces.
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llvm-svn: 22729
2005-08-09 20:21:10 +00:00
6667bdbaca
Update to use the new MathExtras.h support for log2 computation.
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Patch contributed by Jim Laskey!
llvm-svn: 22594
2005-08-02 19:26:06 +00:00
5f4ef3c5a8
Eliminate all remaining tabs and trailing spaces.
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llvm-svn: 22523
2005-07-27 06:12:32 +00:00
53676dfd33
Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode.
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This is the last MVTSDNode.
This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.
Also, remove some uses of dyn_cast that should really be cast (which is
cheaper in a release build).
llvm-svn: 22368
2005-07-10 01:56:13 +00:00
36db1ed06f
Change TRUNCSTORE to use a VTSDNode operand instead of being an MVTSTDNode
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llvm-svn: 22366
2005-07-10 00:29:18 +00:00
a7220851c0
Make several cleanups to Andrews varargs change:
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1. Pass Value*'s into lowering methods so that the proper pointers can be
added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
4. Now that we have Value*'s available in the lowering methods, pass them
into any load/stores from the valist that are emitted
llvm-svn: 22339
2005-07-05 19:58:54 +00:00
f11f48ba61
Refactor the addPassesToEmitAssembly interface into a addPassesToEmitFile
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interface.
llvm-svn: 22282
2005-06-25 02:48:37 +00:00
253145299b
If we support structs as va_list, we must pass pointers to them to va_copy
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See last commit for LangRef, this implements it on all targets.
llvm-svn: 22273
2005-06-22 21:04:42 +00:00
9144ec4764
core changes for varargs
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llvm-svn: 22254
2005-06-18 18:34:52 +00:00
3a5eb61899
re-enable direct calls, this should just be a performance boost
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llvm-svn: 22148
2005-05-20 11:39:17 +00:00
9f406cb29b
make angry compilers happy again
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llvm-svn: 22054
2005-05-15 14:44:13 +00:00
8abab9b0c7
treat TAILCALL nodes identically to CALL nodes
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llvm-svn: 21977
2005-05-13 20:29:26 +00:00
2e77db6af6
Add an isTailCall flag to LowerCallTo
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llvm-svn: 21958
2005-05-13 18:50:42 +00:00
2dce703710
rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN.
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llvm-svn: 21915
2005-05-12 23:24:06 +00:00
36674a123e
Pass in Calling Convention to use into LowerCallTo
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llvm-svn: 21899
2005-05-12 19:56:45 +00:00
25163d8d60
add the popcount instruction and support this in the isel
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the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...
llvm-svn: 21860
2005-05-11 05:16:09 +00:00
669c3b17eb
No really IA*64* :)
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llvm-svn: 21858
2005-05-11 05:03:56 +00:00
74a01fa211
fix and cleanup constmul code a bit, this fixes mediabench/toast and
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probably a couple of other tests.
llvm-svn: 21814
2005-05-09 13:18:34 +00:00
b8e94c3499
fix typo
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llvm-svn: 21693
2005-05-04 19:25:37 +00:00
7acd5d5f06
support multiplication by constant negative integers
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this constmul code is still buggy though, so beware. mul by 7427 is currently
broken, for example. will fix it when I get a moment :)
llvm-svn: 21652
2005-05-02 07:27:14 +00:00
0e73188c10
add support for bools to SELECT, this fixes Prolangs-C/bison from the
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testsuite, however 09-vor is still dead (hopefully for other reasons!)
llvm-svn: 21651
2005-05-02 06:41:13 +00:00
9c6bbafc15
This target doesn't support the FSIN/FCOS/FSQRT nodes yet
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llvm-svn: 21633
2005-04-30 04:26:06 +00:00
4a73c2cfdc
Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.
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(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*. Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.
llvm-svn: 21599
2005-04-27 20:10:01 +00:00
b071bef66a
clean up some warnings
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llvm-svn: 21590
2005-04-27 11:57:39 +00:00
e06ef80244
constmul bugfix: multiply by 27611 was broken
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llvm-svn: 21564
2005-04-26 09:42:50 +00:00
bbd0cd71a8
clean up the code! (oops) lots more cleaning left, however.
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llvm-svn: 21563
2005-04-26 08:43:47 +00:00
81ebb57771
* Add code to reduce multiplies by constant integers to shifts, adds and
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subtracts. This is a very rough and nasty implementation of Lefevre's
"pattern finding" algorithm. With a few small changes though, it should
end up beating most other methods in common use, regardless of the size
of the constant (currently, it's often one or two shifts worse)
TODO: rewrite it so it's not hideously ugly (this is a translation from
perl, which doesn't help ;)
bypass most of it for multiplies by 2^n+1
(eventually) teach it that some combinations of shift+add are
cheaper than others (e.g. shladd on ia64, scaled adds on alpha)
get it to try multiple booth encodings in search of the cheapest
routine
make it work for negative constants
This is hacked up as a DAG->DAG transform, so once I clean it up I hope
it'll be pulled out of here and put somewhere else. The only thing backends
should really have to worry about for now is where to draw the line
between using this code vs. going ahead and doing an integer multiply
anyway.
llvm-svn: 21560
2005-04-26 07:23:02 +00:00
e73e76dc42
Convert tabs to spaces
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llvm-svn: 21452
2005-04-22 17:54:37 +00:00
89b8c8d215
Remove trailing whitespace
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llvm-svn: 21424
2005-04-21 23:13:11 +00:00
0a7c2b9078
print negative 64 bit immediates as negative numbers, makes things a little
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easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything
llvm-svn: 21300
2005-04-14 10:08:01 +00:00
dfbbcc098b
oops, this stopped us turning movl r4=0xFFFFFFFF;; and rX, r4 into zxt4
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llvm-svn: 21299
2005-04-14 10:06:35 +00:00
f6b666fb06
we have zextloads, not sextloads!
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llvm-svn: 21296
2005-04-14 08:37:32 +00:00
2f2312575b
* add the shladd instruction
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* fold left shifts of 1, 2, 3 or 4 bits into adds
This doesn't save much now, but should get a serious workout once
multiplies by constants get converted to shift/add/sub sequences.
Hold on! :)
llvm-svn: 21282
2005-04-13 06:12:04 +00:00
e7ef27bcfe
* if ANDing with a constant of the form:
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0x00000..00FFF..FF
^ ^
^ ^
any number of
0's followed by
some number of
1's
then we use dep.z to just paste zeros over the input. For the special
cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
because we're all about readability!!!
that's what it's about!! readability!
*twitch* ;D
llvm-svn: 21279
2005-04-13 04:50:54 +00:00
7f4c4179a6
Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing
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things like this:
mov r9 = 65535;;
and r8 = r8, r9;;
To be emitted instead of:
zxt2 r8 = r8;;
To get this back, the selector for ISD::AND should recognize this case.
llvm-svn: 21269
2005-04-13 02:41:52 +00:00
fd469bddac
* OK, after changing to use liveIn/liveOut instead of IDEFs,
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to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.
FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:
out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127
and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)
llvm-svn: 21252
2005-04-12 18:42:59 +00:00
14f72885dd
Put out* into the allocation order, allowing the register allocator to
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coallesce moves into outgoing args.
llvm-svn: 21249
2005-04-12 15:12:51 +00:00
6b91767b77
Make sure to realize that calls use their argument regs
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llvm-svn: 21248
2005-04-12 15:12:19 +00:00
b6dfb227b7
stop emitting IDEFs for args - change to using liveIn/liveOut
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llvm-svn: 21247
2005-04-12 14:54:44 +00:00
607bd26b38
IA64 supports this operation.
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llvm-svn: 21228
2005-04-11 18:55:36 +00:00
8de7ac092d
hmm, should probably change addImm() to take 64-bit arguments one day anyway.
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llvm-svn: 21224
2005-04-11 07:16:39 +00:00
fb43ef78c5
assorted fixes:
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* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
* fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
* fix nasty thinko - didn't use two-address form of conditional add
for extending bools to integers, so occasionally there would be
garbage in the result. it's amazing how often zeros are just
sitting around in registers ;) - this should fix a bunch of tests.
llvm-svn: 21221
2005-04-11 05:55:56 +00:00
46aa06cfed
ok, the "ia64 has a boatload of registers" joke stopped being funny today ;)
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* fix overallocation of integer (stacked) registers: we can't allocate
registers for local use if they are required as output registers
this fixes 'toast' in the test suite, and all sorts of larger programs
like bzip2 etc.
llvm-svn: 21178
2005-04-09 11:53:00 +00:00
a3a135a9f7
This target does not support/want ISD::BRCONDTWOWAY
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llvm-svn: 21164
2005-04-09 03:22:37 +00:00
41ff502549
fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn)
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fix hack in division (clean up frcpa instruction)
llvm-svn: 21153
2005-04-08 10:01:48 +00:00
Chris Lattner