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Author SHA1 Message Date
Scott Michel 5ecac82f71 CellSPU testcase, extract_elt.ll: extract vector element. 
llvm-svn: 45219
 2007-12-19 21:17:42 +00:00
Scott Michel 098c113bc8 Two more test cases: or_ops.ll (arithmetic or operations) and vecinsert.ll 
(vector insertions)

llvm-svn: 45216
 2007-12-19 20:15:47 +00:00
Scott Michel 9b834469e0 Add new immed16.ll test case, fix CellSPU errata to make test case work. 
llvm-svn: 45196
 2007-12-19 07:35:06 +00:00
Bill Wendling ca77ecb40a Mark the "isRemat" instruction as never having side effects. 
llvm-svn: 45190
 2007-12-19 06:07:48 +00:00
Chris Lattner 2583a66295 add an obvious load folding missed optzn. 
llvm-svn: 45161
 2007-12-18 16:48:14 +00:00
Christopher Lamb 8b09a464b4 Fold certain additions through selects (and their compares) so as to eliminate subtractions. This code is often produced by the SMAX expansion in SCEV. 
This implements test/Transforms/InstCombine/2007-12-18-AddSelCmpSub.ll

llvm-svn: 45158
 2007-12-18 09:34:41 +00:00
Chris Lattner 52a9e40789 add a missed case. 
llvm-svn: 45141
 2007-12-18 01:19:18 +00:00
Bill Wendling b3d85a5d4b Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I 
based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.

llvm-svn: 45132
 2007-12-17 23:07:56 +00:00
Scott Michel c5cccb9e60 - Restore some i8 functionality in CellSPU 
- New test case: nand.ll

llvm-svn: 45130
 2007-12-17 22:32:34 +00:00
Bill Wendling a2401be121 LD_Fp64m should have "isRematerializable" set. 
llvm-svn: 45128
 2007-12-17 22:17:14 +00:00
Bill Wendling 939526a930 As per feedback, revised comments to (hopefully) make the different side effect 
flags clearer.

llvm-svn: 45120
 2007-12-17 21:02:07 +00:00
Christopher Lamb edf0788758 Change the PointerType api for creating pointer types. The old functionality of PointerType::get() has become PointerType::getUnqual(), which returns a pointer in the generic address space. The new prototype of PointerType::get() requires both a type and an address space. 
llvm-svn: 45082
 2007-12-17 01:12:55 +00:00
Chris Lattner 2af27c202c don't violate C TBAA rules, use FloatToBits instead. 
llvm-svn: 45076
 2007-12-16 20:41:33 +00:00
Chris Lattner e3b05fe31b fix a questionable cast, thanks to Mike Stump for pointing this out. 
llvm-svn: 45075
 2007-12-16 20:26:54 +00:00
Chris Lattner dab6bd902e Fix the JIT encoding of cmp*ss, which aborts with this assertion currently: 
X86CodeEmitter.cpp:378: failed assertion `0 && "Immediate size not set!"'

I *think* this is right, but Evan, please verify.  It also looks like
CMPSDrr and maybe others are missing this info.  Evan, plz investigate.

llvm-svn: 45074
 2007-12-16 20:12:41 +00:00
Evan Cheng 23d2d4dc6c Make better use of instructions that clear high bits; fix various 2-wide shuffle bugs. 
llvm-svn: 45058
 2007-12-15 03:00:47 +00:00
Scott Michel 0aa7133f82 Start committing working test cases for CellSPU. 
llvm-svn: 45050
 2007-12-15 00:38:50 +00:00
Evan Cheng 9556729128 Actually, MOVPQIto64mr is a dup of MOVPQI2QImr, MOV64toPQIrm is a dup of MOVQI2PQIrm. 
llvm-svn: 45041
 2007-12-14 20:08:14 +00:00
Evan Cheng e28372c0d6 Fix (mem) <-> low 64-bits of xmm bugs pointed out by David Greene. Mac OS X Leopard assembler recognizes movq. 
llvm-svn: 45040
 2007-12-14 19:54:07 +00:00
Dale Johannesen f7cefdd5f0 x86-32 long doubles are 4-byte aligned on the stack 
for parameter passing (only for that, on Darwin).

llvm-svn: 45038
 2007-12-14 19:25:34 +00:00
Evan Cheng a56e6ff9a7 Fix bsf / bsr jit encoding. 
llvm-svn: 45037
 2007-12-14 18:49:43 +00:00
Evan Cheng f28c810036 Oops. Forgot these. 
llvm-svn: 45036
 2007-12-14 18:25:34 +00:00
Dan Gohman 9d2e9e376f Fix Intel asm syntax for the bsr and bsf instructions. 
llvm-svn: 45030
 2007-12-14 15:10:00 +00:00
Evan Cheng 0e6408124e Fix ctlz and cttz. llvm definition requires them to return number of bits in of the src type when value is zero. 
llvm-svn: 45029
 2007-12-14 08:30:15 +00:00
Evan Cheng e9fbc3f014 Implement ctlz and cttz with bsr and bsf. 
llvm-svn: 45024
 2007-12-14 02:13:44 +00:00
Bill Wendling cb77f04e1f Add flags to indicate that there are "never" side effects or that there "may be" 
side effects for machine instructions.

llvm-svn: 45022
 2007-12-14 01:48:59 +00:00
Evan Cheng 827d30db19 Fold some and + shift in x86 addressing mode. 
llvm-svn: 44970
 2007-12-13 00:43:27 +00:00
Evan Cheng 6e68381e02 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
llvm-svn: 44960
 2007-12-12 23:12:09 +00:00
Duncan Sands fde556745b Remove host endianness info from TargetData and 
put it in a new header System/Host.h instead.
Instead of getting the endianness from configure,
calculate it directly.

llvm-svn: 44959
 2007-12-12 23:03:45 +00:00
Dan Gohman 7a7742c2fe Allow vector integer constants to be created with 
SelectionDAG::getConstant, in the same way as vector floating-point
constants. This allows the legalize expansion code for @llvm.ctpop and
friends to be usable with vector types.

llvm-svn: 44954
 2007-12-12 22:21:26 +00:00
Evan Cheng 0f42730722 Use shuffles to implement insert_vector_elt for i32, i64, f32, and f64. 
llvm-svn: 44929
 2007-12-12 07:55:34 +00:00
Evan Cheng 2a98956796 Lower a build_vector with all constants into a constpool load unless it can be done with a move to low part. 
llvm-svn: 44921
 2007-12-12 06:45:40 +00:00
Scott Michel 4a8bc7e105 Correct typo for Linux: s/esp/%rsp/ 
llvm-svn: 44904
 2007-12-12 02:38:28 +00:00
Nate Begeman 6dc8b4ed13 Allow the JIT to encode MMX instructions 
llvm-svn: 44869
 2007-12-11 18:06:14 +00:00
Evan Cheng 4fbf459549 - Improved v8i16 shuffle lowering. It now uses pshuflw and pshufhw as much as 
possible before resorting to pextrw and pinsrw.
- Better codegen for v4i32 shuffles masquerading as v8i16 or v16i8 shuffles.
- Improves (i16 extract_vector_element 0) codegen by recognizing
  (i32 extract_vector_element 0) does not require a pextrw.

llvm-svn: 44836
 2007-12-11 01:46:18 +00:00
Nate Begeman a55a67ae91 x86 doesn't actually want to custom lower v3i32 
llvm-svn: 44835
 2007-12-11 01:41:33 +00:00
Chris Lattner 2945c46e93 Move TargetData::hostIsLittleEndian out of line, which means we 
don't have to #include config.h in it.  #including config.h breaks
other projects that have their own autoconf stuff and try to #include
the llvm headers.  One obscure example is llvm-gcc.

llvm-svn: 44825
 2007-12-11 00:28:59 +00:00
Anton Korobeynikov 21ade5880b Hey, English is not my native language :) 
llvm-svn: 44820
 2007-12-10 23:10:20 +00:00
Anton Korobeynikov 77eb5e649d Clarify the need of CFI() stuff 
llvm-svn: 44819
 2007-12-10 23:08:35 +00:00
Anton Korobeynikov a6b0f7e244 Provide convenient way to disable CFI stuff for old/broken assemblers. 
Use it for Darwin.

llvm-svn: 44818
 2007-12-10 23:04:38 +00:00
Chris Lattner 8a72a7d586 Disable cfi directives for now, darwin does't support them. 
These should probably be something like:

  CFI(".cfi_def_cfa_offset 16\n")

where CFI is defined to a noop on darwin and other platforms
that don't support those directives.

llvm-svn: 44803
 2007-12-10 19:10:18 +00:00
Anton Korobeynikov 657be86229 And finally annotate X86-64 version of callback. 
All bad stuff from SSE version is implicitely inherited :)

llvm-svn: 44794
 2007-12-10 15:27:07 +00:00
Anton Korobeynikov 88e9d082d8 Provide annotation for SSE version of callback. It's even more 
broken, because doesn't mark xmm regs properly

llvm-svn: 44793
 2007-12-10 15:13:55 +00:00
Anton Korobeynikov 81e9dc4af7 Annotate JIT callback function with call frame infromation. 
This will allow us (theoretically) to unwind through JITer.
The code wasn't verified, so I'm pretty sure offsets are wrong :)

llvm-svn: 44792
 2007-12-10 14:54:42 +00:00
Bill Wendling 3f19dfe794 Reverting 44702. It wasn't correct to rename them. 
llvm-svn: 44727
 2007-12-08 23:58:46 +00:00
Chris Lattner ff87f05e43 aesthetic changes, no functionality change. Evan, it's not clear 
what 'Available' is, please add a comment near it and rename it
if appropriate.

llvm-svn: 44703
 2007-12-08 07:22:58 +00:00
Bill Wendling 2b07d8c5a0 Renaming: 
isTriviallyReMaterializable -> hasNoSideEffects
  isReallyTriviallyReMaterializable -> isTriviallyReMaterializable

llvm-svn: 44702
 2007-12-08 07:17:56 +00:00
Chris Lattner f47015bc74 Fix a significant code quality regression I introduced on PPC64 quite 
a while ago.  We now produce:

_foo:
	mflr r0
	std r0, 16(r1)
	ld r2, 16(r1)
	std r2, 0(r3)
	ld r0, 16(r1)
	mtlr r0
	blr 

instead of:

_foo:
	mflr r0
	std r0, 16(r1)
	lis r0, 0
	ori r0, r0, 16
	ldx r2, r1, r0
	std r2, 0(r3)
	ld r0, 16(r1)
	mtlr r0
	blr 

for:

void foo(void **X) {
  *X = __builtin_return_address(0);
}

on ppc64.

llvm-svn: 44701
 2007-12-08 07:04:58 +00:00
Chris Lattner f6a8156e4f implement __builtin_return_addr(0) on ppc. 
llvm-svn: 44700
 2007-12-08 06:59:59 +00:00
Chris Lattner a6c8297e84 refactor some code to avoid overloading the name 'usesLR' in 
different places to mean different things.  Document what the
one in PPCFunctionInfo means and when it is valid.

llvm-svn: 44699
 2007-12-08 06:39:11 +00:00
Evan Cheng 92105ac0cd Doh 
llvm-svn: 44694
 2007-12-08 01:01:07 +00:00
Evan Cheng cd6913627e Fix a compilation warning. 
llvm-svn: 44692
 2007-12-08 01:00:31 +00:00
Evan Cheng ab87e735cd Fix a compilation warning. 
llvm-svn: 44691
 2007-12-08 01:00:21 +00:00
Bill Wendling fb706bc52b Initial commit of the machine code LICM pass. It successfully hoists this: 
_foo:
        li r2, 0
LBB1_1: ; bb
        li r5, 0
        stw r5, 0(r3)
        addi r2, r2, 1
        addi r3, r3, 4
        cmplw cr0, r2, r4
        bne cr0, LBB1_1 ; bb
LBB1_2: ; return
        blr 

to:

_foo:
        li r2, 0
        li r5, 0
LBB1_1: ; bb
        stw r5, 0(r3)
        addi r2, r2, 1
        addi r3, r3, 4
        cmplw cr0, r2, r4
        bne cr0, LBB1_1 ; bb
LBB1_2: ; return
        blr

ZOMG!! :-)

Moar to come...

llvm-svn: 44687
 2007-12-07 21:42:31 +00:00
Evan Cheng b41d838d28 Add comment. 
llvm-svn: 44686
 2007-12-07 21:30:01 +00:00
Evan Cheng bfd373a53e Much improved v8i16 shuffles. (Step 1). 
llvm-svn: 44676
 2007-12-07 08:07:39 +00:00
Evan Cheng c829e5cdf0 Remove a bogus optimization. It's not possible to do a move to low element to a <8 x i16> or <16 x i8> vector. 
llvm-svn: 44669
 2007-12-06 22:14:22 +00:00
Chris Lattner 7c709a5d08 implement a readme entry, compiling the code into: 
_foo:
	movl	$12, %eax
	andl	4(%esp), %eax
	movl	_array(%eax), %eax
	ret

instead of:

_foo:
	movl	4(%esp), %eax
	shrl	$2, %eax
	andl	$3, %eax
	movl	_array(,%eax,4), %eax
	ret

As it turns out, this triggers all the time, in a wide variety of
situations, for example, I see diffs like this in various programs:

-       movl    8(%eax), %eax
-       shll    $2, %eax
-       andl    $1020, %eax
-       movl    (%esi,%eax), %eax
+       movzbl  8(%eax), %eax
+       movl    (%esi,%eax,4), %eax


-       shll    $2, %edx
-       andl    $1020, %edx
-       movl    (%edi,%edx), %edx
+       andl    $255, %edx
+       movl    (%edi,%edx,4), %edx

Unfortunately, I also see stuff like this, which can be fixed in the
X86 backend:

-       andl    $85, %ebx
-       addl    _bit_count(,%ebx,4), %ebp
+       shll    $2, %ebx
+       andl    $340, %ebx
+       addl    _bit_count(%ebx), %ebp

llvm-svn: 44656
 2007-12-06 07:33:36 +00:00
Chris Lattner 5e224c32f4 add a note 
llvm-svn: 44638
 2007-12-05 23:05:06 +00:00
Chris Lattner ad05e17491 add a note 
llvm-svn: 44637
 2007-12-05 22:58:19 +00:00
Scott Michel 83d54c9ee0 Minor updates: 
- Fix typo in SPUCallingConv.td
- Credit myself for CellSPU work
- Add CellSPU to 'all' host target list

llvm-svn: 44627
 2007-12-05 21:23:16 +00:00
Evan Cheng 3b8a674469 Added canFoldMemoryOperand for PPC. 
llvm-svn: 44623
 2007-12-05 18:41:29 +00:00
Evan Cheng 8492bdeaa4 Update foldMemoryOperand. 
llvm-svn: 44621
 2007-12-05 18:36:37 +00:00
Chris Lattner de9bfcf67a fix warnings 
llvm-svn: 44620
 2007-12-05 18:32:18 +00:00
Chris Lattner 8292519705 allow this to build 
llvm-svn: 44619
 2007-12-05 18:30:11 +00:00
Evan Cheng bb26301864 Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether 
the stored register is killed.

llvm-svn: 44600
 2007-12-05 03:14:33 +00:00
Scott Michel 4834955fdf More stuff for CellSPU -- this should be enough to get an error-free 
compilation (no files missing). Test cases remain to be checked in.

llvm-svn: 44598
 2007-12-05 02:01:41 +00:00
Scott Michel d1b5b9f68c Updated source file headers to llvm coding standard. 
llvm-svn: 44597
 2007-12-05 01:40:25 +00:00
Scott Michel 8d35728607 Two missing files. 
llvm-svn: 44596
 2007-12-05 01:31:18 +00:00
Scott Michel eff980208a Main CellSPU backend files checked in. Intrinsics and autoconf files 
remain.

llvm-svn: 44595
 2007-12-05 01:24:05 +00:00
Scott Michel dfe09ed085 More files in the CellSPU drop... 
llvm-svn: 44584
 2007-12-04 22:35:58 +00:00
Scott Michel 6e22c651d1 More of the Cell SPU code drop from "Team Aerospace". 
llvm-svn: 44582
 2007-12-04 22:23:35 +00:00
Scott Michel d821fe741e More CellSPU files... more to follow. 
llvm-svn: 44559
 2007-12-03 23:14:43 +00:00
Scott Michel c7bd8d9cb0 Makefile fragment for CellSPU. 
llvm-svn: 44558
 2007-12-03 23:12:49 +00:00
Scott Michel 256e9abbb9 First commit to CellSPU. More to follow 
llvm-svn: 44557
 2007-12-03 23:09:49 +00:00
Duncan Sands 38ef3a8ec7 Rather than having special rules like "intrinsics cannot 
throw exceptions", just mark intrinsics with the nounwind
attribute.  Likewise, mark intrinsics as readnone/readonly
and get rid of special aliasing logic (which didn't use
anything more than this anyway).

llvm-svn: 44544
 2007-12-03 20:06:50 +00:00
Evan Cheng f45a1d623c Remove redundant foldMemoryOperand variants and other code clean up. 
llvm-svn: 44517
 2007-12-02 08:30:39 +00:00
Evan Cheng 69fda0a716 Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0. 
llvm-svn: 44479
 2007-12-01 02:07:52 +00:00
Chris Lattner 246b7b2dbf Work around a GCC bug, producing this code: 
unsigned char *llvm_cbe_X;
...
  llvm_cbe_X = 0; *((void**)&llvm_cbe_X) = __builtin_stack_save();

instead of:

  llvm_cbe_X = __builtin_stack_save();

See PR1809 for details.

llvm-svn: 44415
 2007-11-28 21:26:17 +00:00
Chris Lattner 57ee7c6630 Implement ExpandOperationResult for ppc i64 fp->int, which fixes 
CodeGen/Generic/fp_to_int.ll among others.  Its unclear why this 
just started failing...

llvm-svn: 44407
 2007-11-28 18:44:47 +00:00
Duncan Sands 5208d1ab4a Add some convenience methods for querying attributes, and 
use them.

llvm-svn: 44403
 2007-11-28 17:07:01 +00:00
Chris Lattner 57662f3882 several entries got significantly better, though they still aren't done. 
llvm-svn: 44382
 2007-11-27 22:41:52 +00:00
Chris Lattner f3f4ad9dd6 implement a trivial readme entry. 
llvm-svn: 44380
 2007-11-27 22:36:16 +00:00
Chris Lattner 79ae9895f6 Fix a crash on invalid code due to memcpy lowering. 
llvm-svn: 44378
 2007-11-27 22:14:42 +00:00
Nate Begeman 6f026a654c Support returning non-power-of-2 vectors to unblock some work 
llvm-svn: 44371
 2007-11-27 19:28:48 +00:00
Andrew Lenharth b960acebde something wrong with this opt 
llvm-svn: 44370
 2007-11-27 18:31:30 +00:00
Duncan Sands ad0ea2d430 Fix PR1146: parameter attributes are longer part of 
the function type, instead they belong to functions
and function calls.  This is an updated and slightly
corrected version of Reid Spencer's original patch.
The only known problem is that auto-upgrading of
bitcode files doesn't seem to work properly (see
test/Bitcode/AutoUpgradeIntrinsics.ll).  Hopefully
a bitcode guru (who might that be? :) ) will fix it.

llvm-svn: 44359
 2007-11-27 13:23:08 +00:00
Chris Lattner 5728bdd4db Fix a long standing deficiency in the X86 backend: we would 
sometimes emit "zero" and "all one" vectors multiple times,
for example:

_test2:
	pcmpeqd	%mm0, %mm0
	movq	%mm0, _M1
	pcmpeqd	%mm0, %mm0
	movq	%mm0, _M2
	ret

instead of:

_test2:
	pcmpeqd	%mm0, %mm0
	movq	%mm0, _M1
	movq	%mm0, _M2
	ret

This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type.  This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.

This patch makes the following changes:

1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
   their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
   immAllZerosV in the wrong form now use *_bc to match them with a
   bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle 
   bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
   is legal, instead of generating one that is illegal and expecting
   a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.

This patch is definite goodness, but has the potential to cause random
code quality regressions.  Please be on the lookout for these and let 
me know if they happen.

llvm-svn: 44310
 2007-11-25 00:24:49 +00:00
Chris Lattner 6a49593aa5 add a immAllZerosV_bc pattern fragment for consistency with others. 
llvm-svn: 44303
 2007-11-24 19:02:07 +00:00
Chris Lattner f72ad16263 remove bogus assertion that broke CodeGen/Generic/cast-fp.ll on x86 
among others.

llvm-svn: 44302
 2007-11-24 18:37:20 +00:00
Chris Lattner f81d5886c6 Several changes: 
1) Change the interface to TargetLowering::ExpandOperationResult to 
   take and return entire NODES that need a result expanded, not just
   the value.  This allows us to handle things like READCYCLECOUNTER,
   which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
   ExpandOperationResult.  This makes the result simpler and fully 
   general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
   i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
   allowing them to work with LegalizeDAGTypes.

LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.

llvm-svn: 44300
 2007-11-24 07:07:01 +00:00
Chris Lattner ab98c41337 add a note 
llvm-svn: 44299
 2007-11-24 06:13:33 +00:00
Dale Johannesen e70850cf7b Fix compiler warning. 
llvm-svn: 44261
 2007-11-21 00:45:00 +00:00
Dale Johannesen 763e110a9f Fix .eh table linkage issues on Darwin. Some EH support 
for Darwin PPC, but it's not fully working yet.

llvm-svn: 44258
 2007-11-20 23:24:42 +00:00
Dan Gohman aad83c8ee5 Remove meaningless qualifiers from return types, avoiding compiler warnings. 
llvm-svn: 44240
 2007-11-19 20:46:23 +00:00
Nate Begeman d4d45c268c Add support for vectors to int <-> float casts. 
llvm-svn: 44204
 2007-11-17 03:58:34 +00:00
Anton Korobeynikov 91460e43f1 Implement codegen for flt_rounds on x86 
llvm-svn: 44183
 2007-11-16 01:31:51 +00:00
Evan Cheng 0cbe920d7c Oops. Debugging code shouldn't have been checked in. 
llvm-svn: 44128
 2007-11-14 19:08:32 +00:00
Anton Korobeynikov 2c6387803e Fix PIC jump table codegen on x86-32/linux. In fact, such thing should be applied 
to all targets uses GOT-relative offsets for PIC (Alpha?)

llvm-svn: 44108
 2007-11-14 09:18:41 +00:00
Duncan Sands e2287ed552 Eliminate the recently introduced CCAssignToStackABISizeAlign 
in favour of teaching CCAssignToStack that size 0 and/or align
0 means to use the ABI values.  This seems a neater solution.
It is safe since no legal value type has size 0.

llvm-svn: 44107
 2007-11-14 08:29:13 +00:00
Evan Cheng 7f02cfa599 Clean up sub-register implementation by moving subReg information back to 
MachineOperand auxInfo. Previous clunky implementation uses an external map
to track sub-register uses. That works because register allocator uses
a new virtual register for each spilled use. With interval splitting (coming
soon), we may have multiple uses of the same register some of which are
of using different sub-registers from others. It's too fragile to constantly
update the information.

llvm-svn: 44104
 2007-11-14 07:59:08 +00:00
Dale Johannesen 7904708369 Revert previous; these files aren't ready to go in yet. 
llvm-svn: 44057
 2007-11-13 19:16:02 +00:00
Dale Johannesen 7a7085f6d3 Add parameter to getDwarfRegNum to permit targets 
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.

llvm-svn: 44056
 2007-11-13 19:13:01 +00:00
Evan Cheng c891ae92dc Fix x86-64 jit: remove reliance on Dwarf numbers. 
llvm-svn: 44048
 2007-11-13 17:54:34 +00:00
Bill Wendling 77b13af9a6 Unifacalize the CALLSEQ{START,END} stuff. 
llvm-svn: 44045
 2007-11-13 09:19:02 +00:00
Bill Wendling f359fed9f9 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack 
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037
 2007-11-13 00:44:25 +00:00
Anton Korobeynikov bfb139ec93 Completely forgot, that we have some debug information emission on PPC. This should fix 
some regressions on ppc nightly tests.

llvm-svn: 44029
 2007-11-12 23:36:13 +00:00
Bruno Cardoso Lopes b439132d16 Added JumpTable support 
Fixed some AsmPrinter issues
Added GLOBAL_OFFSET_TABLE Node handle.

llvm-svn: 44024
 2007-11-12 19:49:57 +00:00
Owen Anderson 933b5b7e62 Add a flag for indirect branch instructions. 
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
 2007-11-12 07:39:39 +00:00
Anton Korobeynikov 0644bb865e Clarify the meaning of '-2' register number 
llvm-svn: 43998
 2007-11-11 19:53:50 +00:00
Anton Korobeynikov 4edfea438a Use TableGen to emit information for dwarf register numbers. 
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997
 2007-11-11 19:50:10 +00:00
Dale Johannesen b988e7e8cd Add CCAssignToStackABISizeAlign for convenience in 
dealing with types whose size & alignment are
different on different subtargets.  Use it for x86 f80.

llvm-svn: 43988
 2007-11-10 22:07:15 +00:00
Arnold Schwaighofer d2c16ff905 Update tailcall code to include inline attribute operand for memcpy. 
llvm-svn: 43978
 2007-11-10 10:48:01 +00:00
Evan Cheng fb13fd6f93 Unbreak x86-64 jumptable. 
llvm-svn: 43955
 2007-11-09 19:11:23 +00:00
Anton Korobeynikov 5db5e352b9 Silence a warning 
llvm-svn: 43954
 2007-11-09 19:06:14 +00:00
Dale Johannesen dfb85c7831 Revert previous rewrite per chris's comments. 
llvm-svn: 43950
 2007-11-09 18:07:11 +00:00
Evan Cheng 797d56ff17 Much improved pic jumptable codegen: 
Then:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        imull   $4, %ecx, %ecx
        leal    LJTI1_0-"L1$pb"(%eax), %edx
        addl    LJTI1_0-"L1$pb"(%ecx,%eax), %edx
        jmpl    *%edx

        .align  2
        .set L1_0_set_3,LBB1_3-LJTI1_0
        .set L1_0_set_2,LBB1_2-LJTI1_0
        .set L1_0_set_5,LBB1_5-LJTI1_0
        .set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

Now:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        addl    LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
        jmpl    *%eax

		.align  2
		.set L1_0_set_3,LBB1_3-"L1$pb"
		.set L1_0_set_2,LBB1_2-"L1$pb"
		.set L1_0_set_5,LBB1_5-"L1$pb"
		.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

llvm-svn: 43924
 2007-11-09 01:32:10 +00:00
Dale Johannesen 04fd82088e Rewrite Dwarf number handling per review comments. 
llvm-svn: 43918
 2007-11-09 00:47:10 +00:00
Lauro Ramos Venancio f6a67bf700 [ARM] Implement __builtin_thread_pointer. 
llvm-svn: 43892
 2007-11-08 17:20:05 +00:00
Dale Johannesen 1b9de4dd6f Complete conditionalization of Dwarf reg numbers. 
Would somebody not on Darwin please make sure this
doesn't break anything.  Exception handling failures
would be the most likely symptom.

llvm-svn: 43844
 2007-11-07 21:48:35 +00:00
Dale Johannesen fbe69d2cd6 Interchange Dwarf numbers of ESP and EBP on x86 Darwin. 
Much improvement in exception handling.

llvm-svn: 43794
 2007-11-07 00:25:05 +00:00
Bruno Cardoso Lopes 87bb032c05 Better processor definition 
llvm-svn: 43749
 2007-11-06 03:15:20 +00:00
Rafael Espindola fa0df55bdd Move the LowerMEMCPY and LowerMEMCPYCall to a common place. 
Thanks for the suggestions Bill :-)

llvm-svn: 43742
 2007-11-05 23:12:20 +00:00
Lauro Ramos Venancio 1a30c18e88 [ARM] Fix code generation for: 
static __thread struct {
    int a;
    int b;
} teste = {0, 0};

llvm-svn: 43722
 2007-11-05 18:33:37 +00:00
Evan Cheng 9337929aae Use movups to spill / restore SSE registers on targets where stacks alignment is 
less than 16. This is a temporary solution until dynamic stack alignment is
implemented.

llvm-svn: 43703
 2007-11-05 07:30:01 +00:00
Bruno Cardoso Lopes 3e0d030dad Added support for PIC code with "explicit relocations" *only*. 
Removed all macro code for PIC (goodbye "la").
Support tested with shootout bench.

llvm-svn: 43697
 2007-11-05 03:02:32 +00:00
Duncan Sands 283207a71c Eliminate the remaining uses of getTypeSize. This 
should only effect x86 when using long double.  Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment).  This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.

llvm-svn: 43688
 2007-11-05 00:04:43 +00:00
Chris Lattner 9329e780cd Fix PR1761 by not printing (rip) suffix when in -static mode. 
Evan, please review this.

llvm-svn: 43680
 2007-11-04 19:23:28 +00:00
Nick Lewycky d954dcd138 Fix crash before main on ppc/linux with static constructors. PR1771 
llvm-svn: 43676
 2007-11-04 17:32:10 +00:00
Chris Lattner 296160d443 Fix PR1763 by allowing the 'q' constraint to work with 64-bit 
regs on x86-64.

llvm-svn: 43669
 2007-11-04 06:51:12 +00:00
Evan Cheng 2b93a20b09 Unbreak tailcall opt. 
llvm-svn: 43646
 2007-11-02 17:45:40 +00:00
Chris Lattner 389d430c49 add a note 
llvm-svn: 43642
 2007-11-02 17:04:20 +00:00
Evan Cheng e453ff4913 Missing a getNumOperands check. 
llvm-svn: 43630
 2007-11-02 01:26:22 +00:00
Duncan Sands 44b8721de8 Executive summary: getTypeSize -> getTypeStoreSize / getABITypeSize. 
The meaning of getTypeSize was not clear - clarifying it is important
now that we have x86 long double and arbitrary precision integers.
The issue with long double is that it requires 80 bits, and this is
not a multiple of its alignment.  This gives a primitive type for
which getTypeSize differed from getABITypeSize.  For arbitrary precision
integers it is even worse: there is the minimum number of bits needed to
hold the type (eg: 36 for an i36), the maximum number of bits that will
be overwriten when storing the type (40 bits for i36) and the ABI size
(i.e. the storage size rounded up to a multiple of the alignment; 64 bits
for i36).

This patch removes getTypeSize (not really - it is still there but
deprecated to allow for a gradual transition).  Instead there is:

(1) getTypeSizeInBits - a number of bits that suffices to hold all
values of the type.  For a primitive type, this is the minimum number
of bits.  For an i36 this is 36 bits.  For x86 long double it is 80.
This corresponds to gcc's TYPE_PRECISION.

(2) getTypeStoreSizeInBits - the maximum number of bits that is
written when storing the type (or read when reading it).  For an
i36 this is 40 bits, for an x86 long double it is 80 bits.  This
is the size alias analysis is interested in (getTypeStoreSize
returns the number of bytes).  There doesn't seem to be anything
corresponding to this in gcc.

(3) getABITypeSizeInBits - this is getTypeStoreSizeInBits rounded
up to a multiple of the alignment.  For an i36 this is 64, for an
x86 long double this is 96 or 128 depending on the OS.  This is the
spacing between consecutive elements when you form an array out of
this type (getABITypeSize returns the number of bytes).  This is
TYPE_SIZE in gcc.

Since successive elements in a SequentialType (arrays, pointers
and vectors) need to be aligned, the spacing between them will be
given by getABITypeSize.  This means that the size of an array
is the length times the getABITypeSize.  It also means that GEP
computations need to use getABITypeSize when computing offsets.
Furthermore, if an alloca allocates several elements at once then
these too need to be aligned, so the size of the alloca has to be
the number of elements multiplied by getABITypeSize.  Logically
speaking this doesn't have to be the case when allocating just
one element, but it is simpler to also use getABITypeSize in this
case.  So alloca's and mallocs should use getABITypeSize.  Finally,
since gcc's only notion of size is that given by getABITypeSize, if
you want to output assembler etc the same as gcc then getABITypeSize
is the size you want.

Since a store will overwrite no more than getTypeStoreSize bytes,
and a read will read no more than that many bytes, this is the
notion of size appropriate for alias analysis calculations.

In this patch I have corrected all type size uses except some of
those in ScalarReplAggregates, lib/Codegen, lib/Target (the hard
cases).  I will get around to auditing these too at some point,
but I could do with some help.

Finally, I made one change which I think wise but others might
consider pointless and suboptimal: in an unpacked struct the
amount of space allocated for a field is now given by the ABI
size rather than getTypeStoreSize.  I did this because every
other place that reserves memory for a type (eg: alloca) now
uses getABITypeSize, and I didn't want to make an exception
for unpacked structs, i.e. I did it to make things more uniform.
This only effects structs containing long doubles and arbitrary
precision integers.  If someone wants to pack these types more
tightly they can always use a packed struct.

llvm-svn: 43620
 2007-11-01 20:53:16 +00:00
Bill Wendling b7cabbe295 Silence, accersed warning 
llvm-svn: 43609
 2007-11-01 08:51:44 +00:00
Rafael Espindola 419b6d7ce4 Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold 
and by restructuring the X86 version.

New I just have to move this to a common place :-)

llvm-svn: 43554
 2007-10-31 14:39:58 +00:00
Rafael Espindola 063f177300 Make ARM an X86 memcpy expansion more similar to each other. 
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.

llvm-svn: 43552
 2007-10-31 11:52:06 +00:00
Dale Johannesen b066c1f216 Make i64=expand_vector_elt(v2i64) work in 32-bit mode. 
llvm-svn: 43535
 2007-10-31 00:32:36 +00:00
Dale Johannesen d50c8bcef6 Add missing SSE builtins: CVTPD2PI, CVTPS2PI, 
CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS.

llvm-svn: 43523
 2007-10-30 22:15:38 +00:00
Duncan Sands b508c53c63 Fix for visibility warnings generated by gcc-4.2. 
llvm-svn: 43500
 2007-10-30 13:14:37 +00:00
Dale Johannesen 6aa304e529 Add missing MMX PSUBQ. 
llvm-svn: 43488
 2007-10-30 01:18:38 +00:00
Evan Cheng e106e2f142 Enable more fold (sext (load x)) -> (sext (truncate (sextload x))) 
transformation. Previously, it's restricted by ensuring the number of load uses
is one. Now the restriction is loosened up by allowing setcc uses to be
"extended" (e.g. setcc x, c, eq -> setcc sext(x), sext(c), eq).

llvm-svn: 43465
 2007-10-29 19:58:20 +00:00
Evan Cheng 7b3f7feaea Avoid doing something dumb like rewriting using a 64-bit iv in 32-bit mode. 
llvm-svn: 43446
 2007-10-29 07:57:50 +00:00
Chris Lattner 909a54ccd4 add a note. 
llvm-svn: 43444
 2007-10-29 06:19:48 +00:00
Chris Lattner 5e99fd8c0d Add support for the x86-64 'q' regigster modifier, and add support for the 
b/h/w/k/q inline asm memory modifiers, which are just ignored.  This fixes
PR1748 and CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll

llvm-svn: 43430
 2007-10-29 03:09:07 +00:00
Chris Lattner 9a641510bd Fix PR1749 and InstCombine/2007-10-28-EmptyField.ll by handling 
zero-length fields better.

llvm-svn: 43427
 2007-10-29 02:40:02 +00:00
Evan Cheng c826ac533b New entry. 
llvm-svn: 43420
 2007-10-28 04:01:09 +00:00
Anton Korobeynikov d07d6a411c Fix off-by-one stack offset computations (dwarf information) for callee-saved 
registers in case, when FP pointer was eliminated. This should fixes misc. random
EH-related crahses, when stuff is compiled with -fomit-frame-pointer.
Thanks Duncan for nailing this bug!

llvm-svn: 43381
 2007-10-26 09:13:24 +00:00
Eric Christopher 18063916b5 clo/clz aren't supported on mips I. Keep them around for when we'll 
want them later (mips32/64).

llvm-svn: 43380
 2007-10-26 04:00:13 +00:00
Evan Cheng 7f3d02471d Loosen up iv reuse to allow reuse of the same stride but a larger type when truncating from the larger type to smaller type is free. 
e.g.
Turns this loop:
LBB1_1: # entry.bb_crit_edge
        xorl    %ecx, %ecx
        xorw    %dx, %dx
        movw    %dx, %si
LBB1_2: # bb
        movl    L_X$non_lazy_ptr, %edi
        movw    %si, (%edi)
        movl    L_Y$non_lazy_ptr, %edi
        movw    %dx, (%edi)
		addw    $4, %dx
		incw    %si
		incl    %ecx
		cmpl    %eax, %ecx
		jne     LBB1_2  # bb
	
into

LBB1_1: # entry.bb_crit_edge
        xorl    %ecx, %ecx
        xorw    %dx, %dx
LBB1_2: # bb
        movl    L_X$non_lazy_ptr, %esi
        movw    %cx, (%esi)
        movl    L_Y$non_lazy_ptr, %esi
        movw    %dx, (%esi)
        addw    $4, %dx
		incl    %ecx
        cmpl    %eax, %ecx
        jne     LBB1_2  # bb

llvm-svn: 43375
 2007-10-26 01:56:11 +00:00
Dale Johannesen 65e804a9c3 Support non-POSIX hosts by removing use of strncasecmp. 
llvm-svn: 43364
 2007-10-25 21:54:43 +00:00
Dale Johannesen 10f4152471 Disable a couple more things for ppcf128. 
llvm-svn: 43267
 2007-10-23 23:20:14 +00:00
Evan Cheng ec271b104c Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with right callee-saved defs set for ppc64. 
llvm-svn: 43248
 2007-10-23 06:42:42 +00:00
Evan Cheng 1f2dd35898 Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. 
llvm-svn: 43234
 2007-10-22 22:11:27 +00:00
Dan Gohman bf474959a3 Fix the folding of multiplication into addresses on x86, which was broken 
by the recent {U,S}MUL_LOHI changes.

llvm-svn: 43230
 2007-10-22 20:22:24 +00:00
Evan Cheng bdbed66333 Use ptr type in the immediate field of a BxA instruction so we don't end up selecting 32-bit call instruction for ppc64. 
llvm-svn: 43228
 2007-10-22 19:46:19 +00:00
Evan Cheng c92446af1f Fix an unfolding bug. 
llvm-svn: 43212
 2007-10-22 03:03:20 +00:00
Dale Johannesen 8ee70112ea Allow for copysign having f80 second argument. 
Fixes 5550319.

llvm-svn: 43205
 2007-10-21 01:07:44 +00:00
Evan Cheng 45e096c77e Resolve unfold tables ambiguity. 
llvm-svn: 43194
 2007-10-19 23:50:58 +00:00
Evan Cheng 35ff79370b Local spiller optimization: 
Turn a store folding instruction into a load folding instruction. e.g.
     xorl  %edi, %eax
     movl  %eax, -32(%ebp)
     movl  -36(%ebp), %eax
     orl   %eax, -32(%ebp)
=>
     xorl  %edi, %eax
     orl   -36(%ebp), %eax
     mov   %eax, -32(%ebp)
This enables the unfolding optimization for a subsequent instruction which will
also eliminate the newly introduced store instruction.

llvm-svn: 43192
 2007-10-19 21:23:22 +00:00
Rafael Espindola 18a831d783 split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend. 
llvm-svn: 43176
 2007-10-19 14:35:17 +00:00
Rafael Espindola 846c19dd70 Add support for byval function whose argument is not 32 bit aligned. 
To do this it is necessary to add a "always inline" argument to the
memcpy node. For completeness I have also added this node to memmove
and memset.  I have also added getMem* functions, because the extra
argument makes it cumbersome to use getNode and because I get confused
by it :-)

llvm-svn: 43172
 2007-10-19 10:41:11 +00:00
Chris Lattner b193576bc6 comment fixes 
llvm-svn: 43168
 2007-10-19 04:08:28 +00:00
Chris Lattner 5d979d57ae Add an easy microoptimization I noticed. 
llvm-svn: 43164
 2007-10-19 03:29:26 +00:00
Dale Johannesen 10432e5a67 More ppcf128 issues (maybe the last)? 
llvm-svn: 43160
 2007-10-19 00:59:18 +00:00
Evan Cheng 463e2ab0ac - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. 
- Fix some copy+paste bugs.

llvm-svn: 43153
 2007-10-18 22:40:57 +00:00
Evan Cheng aa9a225699 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. 
llvm-svn: 43150
 2007-10-18 21:29:24 +00:00
Christopher Lamb 79dfbed6f6 Fix a misnamed parameter. 
llvm-svn: 43145
 2007-10-18 19:29:45 +00:00
Christopher Lamb 7f68cf0d57 Fix a typo 
llvm-svn: 43144
 2007-10-18 19:28:55 +00:00
Gordon Henriksen ea31de8dc1 Work around downrev gccs which do not inherit visibility of the 
Registry<>::iterator member class.

llvm-svn: 43122
 2007-10-18 11:53:05 +00:00
Chris Lattner 84f3461c49 legalizing the ret operation on f64 shouldn't introduce a new 
i64 bit convert needlessly.

llvm-svn: 43116
 2007-10-18 06:17:07 +00:00
Gordon Henriksen ef5d08f4ea Switching TargetMachineRegistry to use the new generic Registry. 
llvm-svn: 43094
 2007-10-17 21:28:48 +00:00
Chris Lattner 12d5da49d3 Change fp to sint legalization on x86-32 to do 2 x i32 
loads instead of 1 x i64 loads.  This doesn't change any functionality yet.

llvm-svn: 43068
 2007-10-17 06:17:29 +00:00
Chris Lattner 693cbeadff fix some funny indentation, add comments. 
llvm-svn: 43066
 2007-10-17 06:02:13 +00:00
Dale Johannesen e5530a35d4 Check for invalid cc's in f80 select. 
llvm-svn: 43033
 2007-10-16 18:09:08 +00:00
Chris Lattner 1366653e2f Fix a bug handling frame references in ppc inline asm when the frame offset 
doesn't fit into 16 bits.

llvm-svn: 43032
 2007-10-16 18:00:18 +00:00
Arnold Schwaighofer b3d58b98d0 Correction to tail call optimization code. The new return address 
was stored to the acutal stack slot before the parameters were
lowered to their stack slot. This could cause arguments to be
overwritten by the return address if the called function had less
parameters than the caller function. The update should remove the
last failing test case of llc-beta: SPASS.

llvm-svn: 43027
 2007-10-16 09:05:00 +00:00
Chris Lattner 06a4954e6e Change LowerFP_TO_SINT to create the specific code it needs instead of 
unconditionally creating an i64 bitcast.  With the future legalizer
design, operation legalization can't introduce new nodes with illegal
types.

This fixes the rest of olden on ppc32.

llvm-svn: 43005
 2007-10-15 20:14:52 +00:00
Evan Cheng 7bcfd8f880 LowerFP_TO_SINT must not create a stack object if it's not needed. 
llvm-svn: 43004
 2007-10-15 20:11:21 +00:00
Dale Johannesen 207bd4d90e Handle PPC long double in CBackend. 
llvm-svn: 42972
 2007-10-15 01:05:37 +00:00
Evan Cheng 4099f4f91a Unbreak x86-64. 
llvm-svn: 42962
 2007-10-14 10:09:39 +00:00
Evan Cheng cdf3609130 Revert 42908 for now. 
llvm-svn: 42960
 2007-10-14 05:57:21 +00:00
Dale Johannesen 2f6b6d6fb0 Fix type mismatch error in PPC Altivec (only causes 
a problem when asserts are on).  From vecLib.

llvm-svn: 42959
 2007-10-14 01:58:32 +00:00
Duncan Sands 29af26f147 Clarify that fastcc has a problem with nested function 
trampolines, rather than with nested functions themselves.

llvm-svn: 42955
 2007-10-13 07:38:37 +00:00
Evan Cheng 7082dcf605 Change unfoldMemoryOperand(). User is now responsible for passing in the 
register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.

llvm-svn: 42946
 2007-10-13 02:35:06 +00:00
Arnold Schwaighofer e8d0bf2669 Correcting the corrections. Bad bad baaad emacs! 
llvm-svn: 42935
 2007-10-12 21:53:12 +00:00
Arnold Schwaighofer 1f0da1fefb Corrected many typing errors. And removed 'nest' parameter handling 
for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.

llvm-svn: 42934
 2007-10-12 21:30:57 +00:00
Duncan Sands a6286bd502 Due to the new tail call optimization, trampolines can no 
longer be created for fastcc functions.

llvm-svn: 42925
 2007-10-12 19:37:31 +00:00
Evan Cheng 409fa443fc Update. 
llvm-svn: 42922
 2007-10-12 18:22:55 +00:00
Dan Gohman dc35bd79ca Change the names used for internal labels to use the current 
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908
 2007-10-12 14:53:36 +00:00
Dan Gohman 8d978da3b0 Mark vector ctpop, cttz, and ctlz as Expand on x86. 
llvm-svn: 42905
 2007-10-12 14:09:42 +00:00
Dan Gohman 9013eaff9a Mark vector pow, ctpop, cttz, and ctlz as Expand on PowerPC. 
llvm-svn: 42904
 2007-10-12 14:08:57 +00:00
Evan Cheng 09c0fe0a7f Fold load / store into MOV32to32_ and MOV16to16_. 
llvm-svn: 42895
 2007-10-12 08:38:01 +00:00
Evan Cheng f8c23f074b Flag MOV32to32_ with EXTRACT_SUBREG. They should not be scheduled apart. 
llvm-svn: 42894
 2007-10-12 07:55:53 +00:00
Dan Gohman 482732af9d Set ISD::FPOW to Expand. 
llvm-svn: 42881
 2007-10-11 23:21:31 +00:00
Dale Johannesen 62f65edc32 Add missing argument to PALIGNR 
llvm-svn: 42874
 2007-10-11 20:58:37 +00:00
Arnold Schwaighofer 9ccea99165 Added tail call optimization to the x86 back end. It can be 
enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870
 2007-10-11 19:40:01 +00:00
Chris Lattner d9c9c919da Fix CodeGen/Generic/BasicInstrs.llx on sparc by marking divrem 
illegal.  Thanks to gabor for pointing this out!

llvm-svn: 42832
 2007-10-10 18:10:57 +00:00
Dale Johannesen 666323eacd Next PPC long double bits: ppcf128->i32 conversion. 
Surprisingly complicated.
Adds getTargetNode for 2 outputs, no inputs (missing).

llvm-svn: 42822
 2007-10-10 01:01:31 +00:00
Dan Gohman e8c8ef5234 LowerIntegerDivOrRem no longer exists. 
llvm-svn: 42787
 2007-10-09 15:45:13 +00:00
Dan Gohman 51554bf30e Fix grammar in a comment. 
llvm-svn: 42786
 2007-10-09 15:44:37 +00:00
Dan Gohman 6d28778bfd This is done. 
llvm-svn: 42785
 2007-10-09 15:42:21 +00:00
Evan Cheng 82bc90ac60 Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. 
llvm-svn: 42783
 2007-10-09 07:14:53 +00:00
Bruno Cardoso Lopes 66d9572ced Position Independent Code (PIC) support [3] 
llvm-svn: 42780
 2007-10-09 03:15:11 +00:00
Bruno Cardoso Lopes 35d86e60b6 Position Independent Code (PIC) support [2] 
- Added a function to hold the stack location 
  where GP must be stored during LowerCALL
- AsmPrinter now emits directives based on
  relocation type
- PIC_ set to default relocation type (same as GCC)

llvm-svn: 42779
 2007-10-09 03:01:19 +00:00
Bruno Cardoso Lopes 5cef9cfd09 Position Independent Code (PIC) support [1] 
- Modified instruction format to handle pseudo instructions
- Added LoadAddr SDNode to load symbols.

llvm-svn: 42778
 2007-10-09 02:55:31 +00:00
Evan Cheng f5ec10b64c Bug fix. X86 was emitting redundant setcc and test instructions before a conditional move. 
llvm-svn: 42774
 2007-10-08 22:16:29 +00:00
Dan Gohman a160361c85 Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to 
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
 2007-10-08 18:33:35 +00:00
Evan Cheng 18109c88c3 Allow x86 compare to be commutable by default. 
llvm-svn: 42761
 2007-10-08 18:27:46 +00:00
Dan Gohman 71f0d7d76e When we start enabling SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM in 
target-indepenent lowering, don't use them on PowerPC.

llvm-svn: 42755
 2007-10-08 17:28:24 +00:00
Dan Gohman afedc063ab Simplify getIntPtrType, allowing it to work for arbitrary pointer sizes. 
llvm-svn: 42751
 2007-10-08 15:16:25 +00:00
Chris Lattner b20757d578 disable this entirely: it is causing use of invalidated iterators and infinite looping. 
llvm-svn: 42739
 2007-10-07 22:00:31 +00:00
Chris Lattner 8dd66ab3b2 Fix many regressions on x86 by avoiding dereferencing the end iterator. 
llvm-svn: 42738
 2007-10-07 21:53:12 +00:00
Anton Korobeynikov 67ac2de8bf Oops, I really wanted to commit this part also :) 
llvm-svn: 42700
 2007-10-06 16:39:43 +00:00
Anton Korobeynikov c59496f737 Move merge code into new helper function. 
llvm-svn: 42699
 2007-10-06 16:17:49 +00:00
Evan Cheng f4b5d491df Added DAG xforms. e.g. 
(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.

llvm-svn: 42677
 2007-10-06 02:46:29 +00:00
Dale Johannesen f864ac96d8 Next powerpc long double bits. Comparisons work, 
although not well, and shortening FP converts.

llvm-svn: 42672
 2007-10-06 01:24:11 +00:00
Evan Cheng 1151ffde70 Commute x86 cmove instructions by swapping the operands and change the condition 
to its inverse.
Testing this as llcbeta

llvm-svn: 42661
 2007-10-05 23:13:21 +00:00
Evan Cheng 42a13757de This is done. 
llvm-svn: 42656
 2007-10-05 22:34:59 +00:00
Evan Cheng 484cab7a2f Enable convertToThreeAddress for X86 by default. 
llvm-svn: 42655
 2007-10-05 22:31:10 +00:00
Evan Cheng d3ccf00870 INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still can 
cause performance degradation.

llvm-svn: 42653
 2007-10-05 21:55:32 +00:00
Evan Cheng fa2c828687 In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. 
leal 1(%ecx), %edi, which requires 67H prefix.

llvm-svn: 42647
 2007-10-05 20:34:26 +00:00
Dale Johannesen c0154c06d6 First round of ppc long double. call/return and 
basic arithmetic works.
Rename RTLIB long double functions to distinguish
different flavors of long double; the lib functions
have different names, alas.

llvm-svn: 42644
 2007-10-05 20:04:43 +00:00
Evan Cheng aac0f8e351 Add support to convert more 64-bit instructions to 3-address instructions. 
llvm-svn: 42642
 2007-10-05 18:20:36 +00:00
Evan Cheng 97eba74a52 ADC and SBB uses EFLAGS. 
llvm-svn: 42640
 2007-10-05 17:59:57 +00:00
Dan Gohman 43c29dce18 Change a few more spaces to tabs in assembly output. 
llvm-svn: 42638
 2007-10-05 15:58:41 +00:00
Dan Gohman b074f23dff Change a space to a tab in the assembly output of a .globl directive 
for consistency.

llvm-svn: 42637
 2007-10-05 15:54:58 +00:00
Evan Cheng a8a9c15e30 Testing convertToThreeeAddress as X86 llcbeta. 
llvm-svn: 42630
 2007-10-05 08:04:01 +00:00
Evan Cheng a851e2b92e Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's. 
llvm-svn: 42624
 2007-10-05 01:34:55 +00:00
Evan Cheng 6912b50958 Not needed any more. 
llvm-svn: 42623
 2007-10-05 01:34:14 +00:00
Evan Cheng 1ef9edce5f Forgot these. 
llvm-svn: 42622
 2007-10-05 01:33:45 +00:00
Evan Cheng f4cf5dcdd2 - Added a few target hooks to generate load / store instructions from / to any 
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.

llvm-svn: 42621
 2007-10-05 01:32:41 +00:00
Chris Lattner 1f2b5f0e13 add a note. 
llvm-svn: 42607
 2007-10-04 15:47:27 +00:00
Dan Gohman c731c97fac Use empty() member functions when that's what's being tested for instead 
of comparing begin() and end().

llvm-svn: 42585
 2007-10-03 19:26:29 +00:00
Chris Lattner 4bdb84fe53 add a note 
llvm-svn: 42579
 2007-10-03 17:10:03 +00:00
Chris Lattner 4d4e9cdb62 add a note 
llvm-svn: 42573
 2007-10-03 06:10:59 +00:00
Chris Lattner 21ba176c4b Bill's example is still not enough to repro this, but it has other issues that 
seem significant as well.

llvm-svn: 42564
 2007-10-03 03:40:24 +00:00
Bill Wendling 3efc0758ae Another micro-opt. 
llvm-svn: 42554
 2007-10-02 21:49:31 +00:00
Bill Wendling f214ff8701 Another missed optimization with LICM. 
llvm-svn: 42552
 2007-10-02 21:43:06 +00:00
Bill Wendling 855011e5c6 Small label changes. 
llvm-svn: 42549
 2007-10-02 21:02:53 +00:00
Bill Wendling 4eb7ca4b4c Now with source code. 
llvm-svn: 42548
 2007-10-02 21:01:16 +00:00
Bill Wendling 96ed3bb2d4 Now with LL code! 
llvm-svn: 42547
 2007-10-02 20:54:32 +00:00
Bill Wendling 9c4d61b523 Another missed optimization. 
llvm-svn: 42546
 2007-10-02 20:42:59 +00:00
Bill Wendling 88ea107fdb Micro-optimization -- missed LICM opportunity. 
llvm-svn: 42542
 2007-10-02 19:55:05 +00:00
Dale Johannesen 4d4e77af8e Rewrite sqrt and powi to use anyfloat. By popular demand. 
llvm-svn: 42537
 2007-10-02 17:43:59 +00:00
Evan Cheng 1f79ba6fe6 Refactor code to add load / store folded instructions -> register only 
instructions reverse map.

llvm-svn: 42509
 2007-10-01 23:44:33 +00:00
Evan Cheng a1b7e95039 Typo. X86comi doesn't read / write chain's. 
llvm-svn: 42492
 2007-10-01 18:12:48 +00:00
Dale Johannesen 28e19a48ce Add getABITypeSize, getABITypeSizeInBits 
llvm-svn: 42488
 2007-10-01 16:03:14 +00:00
Gordon Henriksen 0b7cf862bc AsmPrinters overriding getAnalysisUsage should call super. 
And not super's super, either.

llvm-svn: 42482
 2007-09-30 13:39:29 +00:00
Evan Cheng 5fb5a1f389 Enabling new condition code modeling scheme. 
llvm-svn: 42459
 2007-09-29 00:00:36 +00:00
Rafael Espindola 6c04ac1db0 Refactor the memcpy lowering for the x86 target. 
The only generated code difference is that now we call memcpy when
the size of the array is unknown. This matches GCC behavior and is
better since the run time value can be arbitrarily large.

llvm-svn: 42433
 2007-09-28 12:53:01 +00:00
Evan Cheng 1f516560d1 Stop inventing new words. :-) 
llvm-svn: 42429
 2007-09-28 01:35:02 +00:00
Evan Cheng edfc5b2204 Pessimisively assume ADJCALLSTACKDOWN / ADJCALLSTACKUP (which becomes sub / add) clobbers EFLAGS. 
llvm-svn: 42426
 2007-09-28 01:19:48 +00:00
Dan Gohman a1d46c7d0a TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets 
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.

llvm-svn: 42419
 2007-09-27 23:12:31 +00:00
Evan Cheng 99dc695da5 Use GR64 in 64-bit mode. 
llvm-svn: 42417
 2007-09-27 21:50:05 +00:00
Evan Cheng 5a71402be6 Doh. Calls clobber EFLAGS. 
llvm-svn: 42413
 2007-09-27 19:01:55 +00:00
Dale Johannesen 34aa41c475 Make temporaries explicit to avoid premature 
destruction of compiler-created ones.

llvm-svn: 42383
 2007-09-26 23:20:33 +00:00
Evan Cheng 8e136a9dc4 - Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo. 
- Added ability to emit cross class register copies to the BBRU scheduler.
- More aggressive backtracking.

llvm-svn: 42375
 2007-09-26 21:36:17 +00:00
Evan Cheng 8728c3376a - Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from). 
- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.

llvm-svn: 42372
 2007-09-26 21:31:07 +00:00
Evan Cheng b93de587cb Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf. 
llvm-svn: 42371
 2007-09-26 21:28:00 +00:00
Dale Johannesen b6d56401aa Enable codegen for long double abs, sin, cos 
llvm-svn: 42368
 2007-09-26 21:10:55 +00:00
Evan Cheng b4b352656a Typos: POPQ -> POPFQ, POPD -> POPFD. 
llvm-svn: 42348
 2007-09-26 06:38:29 +00:00
Chris Lattner c9e7b8ec50 move PR1160 here. 
llvm-svn: 42347
 2007-09-26 06:29:31 +00:00
Evan Cheng c1e4e3743b Allow copyRegToReg to emit cross register classes copies. 
Tested with "make check"!

llvm-svn: 42346
 2007-09-26 06:25:56 +00:00
Chris Lattner fef69f5b4a move PR1264 here. 
llvm-svn: 42345
 2007-09-26 06:15:48 +00:00
Evan Cheng 0a6f47cff9 Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register. 
llvm-svn: 42335
 2007-09-26 01:29:06 +00:00
Evan Cheng 9b7f0e6eb4 translateX86CC updates the last two operands. 
llvm-svn: 42333
 2007-09-26 00:45:55 +00:00
Anton Korobeynikov e291f727e3 Correctly restore stack pointer after realignment in main() on Cygwin/Mingw32 
llvm-svn: 42332
 2007-09-26 00:13:34 +00:00
Evan Cheng 5321fa44f4 Missing load / store folding entries. 
llvm-svn: 42323
 2007-09-25 22:10:43 +00:00
Anton Korobeynikov 90910745bb Partly revert invalid r41774 
llvm-svn: 42322
 2007-09-25 21:52:30 +00:00
Dan Gohman 57211c5550 More explicit keywords. 
llvm-svn: 42316
 2007-09-25 20:27:06 +00:00
Dan Gohman 06919e8ef2 Fix a typo in a comment. 
llvm-svn: 42313
 2007-09-25 19:37:26 +00:00
Evan Cheng 8ee1ecfc50 New style x87 cmp instructions. 
llvm-svn: 42312
 2007-09-25 19:08:02 +00:00
Dan Gohman 31599685c7 When both x/y and x%y are needed (x and y both scalar integer), compute 
both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.

llvm-svn: 42308
 2007-09-25 18:23:27 +00:00
Dan Gohman 5e1a428344 Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) and 
the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.

llvm-svn: 42297
 2007-09-25 15:10:49 +00:00
Evan Cheng e95f391ef1 Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after 
all the kinks are worked out.

llvm-svn: 42285
 2007-09-25 01:57:46 +00:00
Evan Cheng 8a7dec736d New temporary option -new-cc-modeling-scheme to test the new cc modeling scheme. 
llvm-svn: 42283
 2007-09-25 01:50:04 +00:00
Evan Cheng 43686dad3d Rename keyword "modify" -> "implicit". 
llvm-svn: 42282
 2007-09-25 01:48:59 +00:00
Dale Johannesen 0241bb57b2 When mixing SSE and x87 codegen, it's possible to 
have situations where an SSE instruction turns into
multiple blocks, with the live range of an x87
register crossing them.  To do this correctly make
sure we examine all blocks when inserting
FP_REG_KILL.  PR 1697.  (This was exposed by my
fix for PR 1681, but the same thing could happen
mixing x87 long double with SSE.)

llvm-svn: 42281
 2007-09-24 22:52:39 +00:00
Dan Gohman 1b2156fcae Add support on x86 for having Legalize lower ISD::LOCATION to ISD::DEBUG_LOC 
instead of ISD::LABEL with a manual .debug_line entry when the assembler
supports .file and .loc directives.

llvm-svn: 42278
 2007-09-24 21:54:14 +00:00
Dan Gohman 0cc9d1b93b Merge hasDotLoc and hasDotFile into hasDotLocAndDotFile since .loc and .file 
aren't really usable without each other. 

llvm-svn: 42274
 2007-09-24 21:09:53 +00:00
Bruno Cardoso Lopes 6d5ada23db Added "LoadEffective" pattern to handle stack locations. 
Fixed some comments

llvm-svn: 42271
 2007-09-24 20:15:11 +00:00
Dan Gohman 071efe28bb Fix the syntax for the .loc directive in preparation for using it. 
llvm-svn: 42268
 2007-09-24 19:25:06 +00:00
Dan Gohman 82dcfd2dab The code that used the StartLabelId label was removed, so remove the 
code that creates the label too.

llvm-svn: 42265
 2007-09-24 16:44:26 +00:00
Chris Lattner 5b5484db63 claim that "st" is from the 80-bit register file. This causes x87-using inline 
asm to die with:

ScheduleDAG.cpp:269: failed assertion `false && "Couldn't find the register class"'

instead of:
failed assertion `RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"'

yay.

llvm-svn: 42259
 2007-09-24 05:27:37 +00:00
Dale Johannesen e36c400255 Fix PR 1681. When X86 target uses +sse -sse2, 
keep f32 in SSE registers and f64 in x87.  This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.

llvm-svn: 42246
 2007-09-23 14:52:20 +00:00
Chris Lattner e48195e0f3 Fix PR1679, by printing GEP indices as signed values instead of unsigned. 
llvm-svn: 42239
 2007-09-22 20:16:48 +00:00
Rafael Espindola 4730c04904 Don't add a default STACK_ALIGN (use the generic ABI alignment) 
Implement calls to functions with byval arguments on X86

llvm-svn: 42192
 2007-09-21 15:50:22 +00:00
Rafael Espindola f065f0e2a1 small cleanup: use LowerMemArgument in LowerFastCCArguments also 
llvm-svn: 42189
 2007-09-21 14:55:38 +00:00
Evan Cheng 1ff71872c2 Honor user-defined section specification of a global, ignores whether its initializer is null. 
llvm-svn: 42182
 2007-09-21 00:41:19 +00:00
Devang Patel d29f938335 Do not override user specified section. 
llvm-svn: 42179
 2007-09-20 23:07:37 +00:00
Dan Gohman 4dbc582a36 Fix several more entries in the x86 reload/remat folding tables. 
llvm-svn: 42162
 2007-09-20 14:17:21 +00:00
Dale Johannesen 95be037d67 another long double buglet 
llvm-svn: 42159
 2007-09-20 01:27:54 +00:00
Evan Cheng 8010320365 Enable if-conversion for ARM by default. 
llvm-svn: 42156
 2007-09-20 00:48:22 +00:00
Dale Johannesen 7d67e547b5 More long double fixes. x86_64 should build now. 
llvm-svn: 42155
 2007-09-19 23:55:34 +00:00
Evan Cheng d0e360e16e Avoid referencing deleted instruction. 
llvm-svn: 42153
 2007-09-19 21:48:07 +00:00
Evan Cheng 513874cf3c PSHUFDmi, etc. are actually folding a load, not a store. 
llvm-svn: 42147
 2007-09-19 19:02:47 +00:00
Evan Cheng 17f589f76e Set CCR (EFLAGS) copy cost to -1, i.e. extremely expensive to copy. 
llvm-svn: 42124
 2007-09-19 01:36:39 +00:00
Evan Cheng f73fb6261b Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value 
between two registers in the specific class.

llvm-svn: 42123
 2007-09-19 01:35:01 +00:00
Dan Gohman 8cca8469de Move the entries for 64-bit CMP, IMUL, and a few others into the correct 
tables so that they are eligible for reload/remat folding. And add
entries for JMP and CALL.

llvm-svn: 42094
 2007-09-18 14:59:14 +00:00
Dale Johannesen ff7e443792 Remove RSTRegClass case from loadRegFromStackSlot 
and storeRegToStackSlot.  Evan and I concluded this
should never be needed and it appears to be true.
(It if is needed, adjustment would be needed for
long double to work.)

llvm-svn: 42049
 2007-09-17 20:15:38 +00:00
Chris Lattner 0625bd6472 Merge DenseMapKeyInfo & DenseMapValueInfo into DenseMapInfo 
Add a new DenseMapInfo::isEqual method to allow clients to redefine
the equality predicate used when probing the hash table.

llvm-svn: 42042
 2007-09-17 18:34:04 +00:00
Evan Cheng 8070099fef X86ISD::TEST is dead. 
llvm-svn: 42037
 2007-09-17 17:42:53 +00:00
Dan Gohman 3243e10ef0 Add 64-bit jmp instructions to the list of instructions that 
can terminate a block with no fall-through.

llvm-svn: 42029
 2007-09-17 15:19:08 +00:00
Dan Gohman 96aee15d33 Use xorl instead of xorq to enter a zero into a 64-bit register. 
llvm-svn: 42027
 2007-09-17 14:55:08 +00:00
Dan Gohman 863bdc332d Emit integer x<1 as x<=0, as comparisons with zero (now includeing 
64-bit) can use test instead of cmp with an immediate.

llvm-svn: 42026
 2007-09-17 14:49:27 +00:00
Dan Gohman 51d1929b9e Use "test reg,reg" in place of "cmp reg,0" for 64-bit operands. This was 
previously only done for 32-bit and smaller operands.

llvm-svn: 42024
 2007-09-17 14:35:24 +00:00
Dale Johannesen 7511e6b622 Implement x86 long double (uses host long double, 
so only works on x86 target).

llvm-svn: 42019
 2007-09-17 00:38:27 +00:00
Bill Wendling 327e1a386c Follow-up to patch r41999. Make the conditional that emits the personality stub 
match the conditional that turns on exception handling emittion in the asm
printer.

llvm-svn: 42008
 2007-09-16 19:21:08 +00:00
Bill Wendling e5615156cc Only emit the personality function as a global value if the backend actually 
supports it. This solves this error on the Darwin x86-64 platform:

$ cat testcase.ii
struct A {
  A();
};

A *bork() {
  return new A;
}
$ llvm-g++ -arch x86_64 -c testcase.ii
/var/tmp//cc3U8fd8.s:52:unknown section type: non_lazy_symbol_pointers
/var/tmp//cc3U8fd8.s:52:Rest of line ignored. 1st junk character valued 76 (L).
/var/tmp//cc3U8fd8.s:53:Unknown pseudo-op: .indirect_symbol
/var/tmp//cc3U8fd8.s:53:Rest of line ignored. 1st junk character valued 95 (_).

llvm-svn: 41999
 2007-09-16 10:36:17 +00:00
Chris Lattner 4f230451e1 Fix PR1666, SPASS with the CBE and 254.gap with the CBE. 
GCC optimizes away things like ptr < NULL  to false.  To "fix" this,
have the CBE emit casts of pointers to intptr_t when doing relational
pointer comparisons.

llvm-svn: 41983
 2007-09-15 06:51:03 +00:00
Dan Gohman 48ea03d169 Add patterns for SHLD64* and SHRD64*. 
llvm-svn: 41975
 2007-09-14 23:17:45 +00:00
Dale Johannesen 98d3a08d8f Remove the assumption that FP's are either float or 
double from some of the many places in the optimizers
it appears, and do something reasonable with x86
long double.
Make APInt::dump() public, remove newline, use it to
dump ConstantSDNode's.
Allow APFloats in FoldingSet.
Expand X86 backend handling of long doubles (conversions
to/from int, mostly).

llvm-svn: 41967
 2007-09-14 22:26:36 +00:00
Evan Cheng 483e1ce16e Add implicit def of EFLAGS on those instructions that may modify flags. 
llvm-svn: 41962
 2007-09-14 21:48:26 +00:00
Dan Gohman 9da02f5ee2 Remove isReg, isImm, and isMBB, and change all their users to use 
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958
 2007-09-14 20:33:02 +00:00
Rafael Espindola 272f7304f0 Add support for functions with byval arguments on x86 
llvm-svn: 41953
 2007-09-14 15:48:13 +00:00
Evan Cheng 5196f617a1 Fix comments. 
llvm-svn: 41947
 2007-09-14 01:57:02 +00:00
Evan Cheng 59c39dc197 Initial support for multi-result patterns: 
1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.

llvm-svn: 41897
 2007-09-12 23:30:14 +00:00
Dale Johannesen 028084efe5 Revise previous patch per review comments. 
Next round of x87 long double stuff.
Getting close now, basically works.

llvm-svn: 41875
 2007-09-12 03:30:33 +00:00
Bill Wendling 66c22e8fd6 Enable indirect encoding for the personality function 
llvm-svn: 41873
 2007-09-11 23:55:40 +00:00
Evan Cheng 3e18e504ae Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Evan Cheng 50b6730ae4 Added status flags register: EFLAGS. 
llvm-svn: 41862
 2007-09-11 19:53:28 +00:00
Dale Johannesen 245dceb06d Add APInt interfaces to APFloat (allows directly 
access to bits).  Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling 
(untested, probably does not work).

llvm-svn: 41858
 2007-09-11 18:32:33 +00:00
Bill Wendling 74fb0f1a1c Add a bool to indicate if we should set the "indirect encoding" bit in the Dwarf 
information for EH.

llvm-svn: 41852
 2007-09-11 17:20:55 +00:00
Duncan Sands 86e0119822 Fold the adjust_trampoline intrinsic into 
init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841
 2007-09-11 14:10:23 +00:00
Duncan Sands 1a11e1c14f My compiler warns about the semicolon. 
llvm-svn: 41840
 2007-09-11 12:30:25 +00:00
Bill Wendling 2b8fc31df9 The personality function on Darwin needs a global stub. We then refer to 
that global stub instead of doing the ".set" thingy we were doing before.

llvm-svn: 41838
 2007-09-11 08:27:17 +00:00
Evan Cheng f948772f9e 80 col. 
llvm-svn: 41812
 2007-09-10 22:22:23 +00:00
Evan Cheng 8c3c198499 New entry. 
llvm-svn: 41810
 2007-09-10 22:16:37 +00:00
Chris Lattner 6777b72659 Add some notes about better flag handling. 
llvm-svn: 41808
 2007-09-10 21:43:18 +00:00
Evan Cheng 637395e6bd It's not safe to rematerialize MOV32r0 etc. by simply cloning the original 
instruction. These are implemented with xor which will modify the conditional
code. They should be rematerialized as move instructions.

llvm-svn: 41802
 2007-09-10 20:48:53 +00:00
Evan Cheng cef2c0efcc TableGen no longer emit CopyFromReg nodes for implicit results in physical 
registers. The scheduler is now responsible for emitting them.

llvm-svn: 41781
 2007-09-07 23:59:02 +00:00
Bill Wendling 9929bc403d Add missing index versions of instructions to the map. 
llvm-svn: 41776
 2007-09-07 22:01:02 +00:00
Dan Gohman a95cbb0007 Avoid storing and reloading zeros and other constants from stack slots 
by flagging the associated instructions as being trivially rematerializable.

llvm-svn: 41775
 2007-09-07 21:32:51 +00:00
Dale Johannesen 9e70086c8f Apply feedback from previous patch. 
llvm-svn: 41774
 2007-09-07 21:07:57 +00:00
Rafael Espindola 1de0c86717 Add support for having different alignment for objects on call frames. 
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.

llvm-svn: 41768
 2007-09-07 14:52:14 +00:00
Owen Anderson e2f23a3abf Add lengthof and endof templates that hide a lot of sizeof computations. 
Patch by Sterling Stein!

llvm-svn: 41758
 2007-09-07 04:06:50 +00:00
Dale Johannesen bed9dc423c Next round of APFloat changes. 
Use APFloat in UpgradeParser and AsmParser.
Change all references to ConstantFP to use the
APFloat interface rather than double.  Remove
the ConstantFP double interfaces.
Use APFloat functions for constant folding arithmetic
and comparisons.
(There are still way too many places APFloat is
just a wrapper around host float/double, but we're
getting there.)

llvm-svn: 41747
 2007-09-06 18:13:44 +00:00
Evan Cheng 189df733ed Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen: 
leal    (,%rcx,8), %rcx
It should be
leal    (,%rcx,8), %ecx

llvm-svn: 41735
 2007-09-06 00:14:41 +00:00
Bill Wendling b65ef38590 LVXL and STVXL are also a load and store resp. 
llvm-svn: 41733
 2007-09-05 23:47:12 +00:00
Bill Wendling b9bf812ba5 Add the 64-bit versions of the DS* Altivec instructions. 
llvm-svn: 41717
 2007-09-05 04:05:20 +00:00
Evan Cheng 4dbd9f254a Fix for PR1613: added 64-bit rotate left PPC instructions and patterns. 
llvm-svn: 41711
 2007-09-04 20:20:29 +00:00
Evan Cheng 623dd88775 Mac OS X X86-64 ABI is same as the standard. 
llvm-svn: 41700
 2007-09-04 16:44:41 +00:00
Anton Korobeynikov 50ab26e835 Reapply r41578 with proper fix 
llvm-svn: 41680
 2007-09-03 00:36:06 +00:00
Dale Johannesen da7469f2b5 Revise per review of previous patch. 
llvm-svn: 41645
 2007-08-31 17:03:33 +00:00
Rafael Espindola e636fc05d6 Initial support for calling functions with byval arguments on x86-64 
llvm-svn: 41643
 2007-08-31 15:06:30 +00:00
Rafael Espindola bb8a5cff67 Align i64 and f64 at 8 byte on x86-64. 
This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf

llvm-svn: 41642
 2007-08-31 12:23:58 +00:00
Dale Johannesen 3cf889f75e Enhance APFloat to retain bits of NaNs (fixes oggenc). 
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632
 2007-08-31 04:03:46 +00:00
Raul Herbster ab871baaf8 Instruction formats added used to generate multiply instructions of V5TE. 
llvm-svn: 41629
 2007-08-30 23:34:14 +00:00
Raul Herbster ff32b62942 Unused relocation type reloc_arm_absolute removed. 
llvm-svn: 41628
 2007-08-30 23:31:35 +00:00