fb3cdd83b0
Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.
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Patch by Chris Lidbury.
llvm-svn: 163321
2012-09-06 15:17:49 +00:00
262f6f564f
Use correct part of complex operand to encode VST1 alignment.
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Patch by Chris Lidbury.
llvm-svn: 163318
2012-09-06 14:36:55 +00:00
b4e1ba7191
ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.
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These tests weren't actually being run before (missing ':' after CHECK).
llvm-svn: 161800
2012-08-13 22:25:44 +00:00
6a43bf7d74
Fix #13035 , a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.
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llvm-svn: 161162
2012-08-02 08:29:50 +00:00
288e1af8c8
Fix #13138 , a bug around ARM instruction DSB encoding and decoding issue.
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llvm-svn: 161161
2012-08-02 08:21:27 +00:00
10dd40e42d
Fix #13241 , a bug around shift immediate operand for ARM instruction ADR.
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llvm-svn: 161159
2012-08-02 08:13:13 +00:00
c7690ac7ac
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms.
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llvm-svn: 160775
2012-07-26 07:48:28 +00:00
01deb5f2df
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
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llvm-svn: 160420
2012-07-18 04:11:12 +00:00
a13cd0666e
Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.
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Patch by Vladimir Medic.
llvm-svn: 160143
2012-07-12 21:19:32 +00:00
1dc44dcedd
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
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llvm-svn: 159989
2012-07-10 12:51:09 +00:00
be41e2daa6
Reverse assembler/disassembler operand order for gather instructions.
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llvm-svn: 159983
2012-07-10 06:38:33 +00:00
9bf2b5677d
Reapply r158846.
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Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.
llvm-svn: 159953
2012-07-09 18:46:47 +00:00
b577ff116d
revert r159851.
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llvm-svn: 159854
2012-07-06 20:16:48 +00:00
cfa35fa0ff
Reapply r158846.
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Include file MipsGenRegisterInfo.inc.
llvm-svn: 159851
2012-07-06 19:29:11 +00:00
ff123d5c63
Fix the remaining TCL-style quotes found in the testsuite. This is
...
another mechanical change accomplished though the power of terrible Perl
scripts.
I have manually switched some "s to 's to make escaping simpler.
While I started this to fix tests that aren't run in all configurations,
the massive number of tests is due to a really frustrating fragility of
our testing infrastructure: things like 'grep -v', 'not grep', and
'expected failures' can mask broken tests all too easily.
Essentially, I'm deeply disturbed that I can change the testsuite so
radically without causing any change in results for most platforms. =/
llvm-svn: 159547
2012-07-02 19:09:46 +00:00
5da53436d5
Convert the uses of '|&' to use '2>&1 |' instead, which works on old
...
versions of Bash. In addition, I can back out the change to the lit
built-in shell test runner to support this.
This should fix the majority of fallout on Darwin, but I suspect there
will be a few straggling issues.
llvm-svn: 159544
2012-07-02 18:37:59 +00:00
a5a29f970e
Convert all tests using TCL-style quoting to use shell-style quoting.
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This was done through the aid of a terrible Perl creation. I will not
paste any of the horrors here. Suffice to say, it require multiple
staged rounds of replacements, state carried between, and a few
nested-construct-parsing hacks that I'm not proud of. It happens, by
luck, to be able to deal with all the TCL-quoting patterns in evidence
in the LLVM test suite.
If anyone is maintaining large out-of-tree test trees, feel free to poke
me and I'll send you the steps I used to convert things, as well as
answer any painful questions etc. IRC works best for this type of thing
I find.
Once converted, switch the LLVM lit config to use ShTests the same as
Clang. In addition to being able to delete large amounts of Python code
from 'lit', this will also simplify the entire test suite and some of
lit's architecture.
Finally, the test suite runs 33% faster on Linux now. ;]
For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s
llvm-svn: 159525
2012-07-02 12:47:22 +00:00
98a5bf24a9
X86: add more GATHER intrinsics in LLVM
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Corrected type for index of llvm.x86.avx2.gather.d.pd.256
from 256-bit to 128-bit.
Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256
from 256-bit to 128-bit.
Support the following intrinsics:
llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q
llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256
llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d
llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256
llvm-svn: 159402
2012-06-29 00:54:20 +00:00
a09820414a
X86: add GATHER intrinsics (AVX2) in LLVM
...
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
llvm-svn: 159221
2012-06-26 19:47:59 +00:00
87505f46ac
Revert r158846.
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llvm-svn: 158855
2012-06-20 21:19:39 +00:00
da448fe0b1
In MipsDisassembler.cpp, instead of defining register class tables, use the ones
...
that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.
Also, fix bug in function DecodeAFGR64RegisterClass.
Patch by Vladimir Medic.
llvm-svn: 158846
2012-06-20 20:39:23 +00:00
f1ef87ddbb
Correct decoder for T1 conditional B encoding
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llvm-svn: 158055
2012-06-06 09:12:53 +00:00
c13ed945aa
Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.
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llvm-svn: 157725
2012-05-31 00:49:56 +00:00
ef479ea854
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
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This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
llvm-svn: 157634
2012-05-29 19:05:25 +00:00
ddc67a7655
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
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llvm-svn: 156609
2012-05-11 09:28:27 +00:00
914223010c
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
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for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
llvm-svn: 156118
2012-05-03 22:41:56 +00:00
9560af848c
Fixed disassembler for vstm/vldm ARM VFP instructions.
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llvm-svn: 156077
2012-05-03 16:38:40 +00:00
0fc56890ba
Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
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llvm-svn: 155983
2012-05-02 09:43:18 +00:00
6cff5ad411
Missed some register numbers.
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llvm-svn: 155706
2012-04-27 12:21:46 +00:00
b1a17c425a
Update edis test for r155704.
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llvm-svn: 155705
2012-04-27 12:14:03 +00:00
8a8e9d1b63
Specify cpu to unbreak tests.
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llvm-svn: 155604
2012-04-26 01:38:10 +00:00
70be447e5c
Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
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instructions.
llvm-svn: 155453
2012-04-24 17:45:56 +00:00
c8d223e41e
Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)
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instructions.
llvm-svn: 155444
2012-04-24 15:55:00 +00:00
ca45af9a75
Added support for disassembling unpredictable swp/swpb ARM instructions.
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llvm-svn: 155004
2012-04-18 14:18:57 +00:00
d5c6a63a50
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
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llvm-svn: 155002
2012-04-18 14:09:07 +00:00
41f1fcd80e
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
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llvm-svn: 155001
2012-04-18 13:12:50 +00:00
a2944116dc
Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
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llvm-svn: 155000
2012-04-18 13:02:55 +00:00
9da1918c84
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.
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llvm-svn: 154999
2012-04-18 12:48:43 +00:00
71928e681b
Add disassembler to MIPS.
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Patch by Vladimir Medic.
llvm-svn: 154935
2012-04-17 18:03:21 +00:00
29ae538647
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
...
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
llvm-svn: 154884
2012-04-17 00:49:27 +00:00
def81b9155
Add -disassemble support for -show-inst and -show-encode capability llvm-mc. Also refactor so all MC paraphernalia are created once for all uses as much as possible.
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The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use.
llvm-svn: 154809
2012-04-16 11:32:10 +00:00
72f18bbcff
Fixed a case of ARM disassembly getting an assert on a bad encoding
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of a VST instruction.
llvm-svn: 154544
2012-04-11 22:40:17 +00:00
74c282b5ef
Add retw and lretw instructions. Also, fix Intel syntax parsing for all
...
ret instructions.
llvm-svn: 154468
2012-04-11 01:10:53 +00:00
d2980cd041
Fix ARM disassembly of VLD instructions with writebacks. And add test a case
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for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .
llvm-svn: 154459
2012-04-11 00:25:40 +00:00
aca6c822e6
Fix a number of problems with ARM fused multiply add/subtract instructions.
...
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676
llvm-svn: 154456
2012-04-11 00:13:00 +00:00
4eb9616b24
Add the tests that were supposed to go with r153935 that I forgot svn add
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llvm-svn: 154165
2012-04-06 07:09:59 +00:00
af3c79f0ac
Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.
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llvm-svn: 154101
2012-04-05 16:19:29 +00:00
d365397daa
Added support for handling unpredictable arithmetic instructions on ARM.
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llvm-svn: 154100
2012-04-05 16:13:15 +00:00
7629d63bc4
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
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llvm-svn: 153935
2012-04-03 05:20:24 +00:00
d19f025374
Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler.
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llvm-svn: 153926
2012-04-03 03:01:13 +00:00
55059262aa
Revert r153924. There were buildbot failures.
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llvm-svn: 153925
2012-04-03 02:51:09 +00:00
e2498d014b
MIPS disassembler support.
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Patch by Vladimir Medic.
llvm-svn: 153924
2012-04-03 02:20:58 +00:00
ac37acd31b
Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.
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llvm-svn: 153874
2012-04-02 15:20:39 +00:00
f33086052d
Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
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* Removed test/lib/llvm.exp - it is no longer needed
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
left in the test suite so this code is no longer required. test/lit.cfg is
now much shorter and clearer
* Removed a lot of duplicate code in lit.local.cfg files that need access to
the root configuration, by adding a "root" attribute to the TestingConfig
object. This attribute is dynamically computed to provide the same
information as was previously provided by the custom getRoot functions.
* Documented the config.root attribute in docs/CommandGuide/lit.pod
llvm-svn: 153408
2012-03-25 09:02:19 +00:00
4afd7d2316
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
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llvm-svn: 153252
2012-03-22 14:14:49 +00:00
d213f2111a
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
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llvm-svn: 153251
2012-03-22 13:24:43 +00:00
a6ea32afdd
Added soft fail cases for the disassembler when decoding MUL instructions on ARM.
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llvm-svn: 153250
2012-03-22 13:14:39 +00:00
7e7d5eefb2
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
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case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
llvm-svn: 153218
2012-03-21 20:54:32 +00:00
32a49333ec
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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llvm-svn: 153089
2012-03-20 15:54:56 +00:00
987cef1fe2
Change the second line of the test added for r152414 to use CHECK-NEXT.
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Suggestion by Bill Wendling!
llvm-svn: 152582
2012-03-12 21:38:09 +00:00
ebb10df441
Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.
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Patch by Kay Tiong Khoo!
llvm-svn: 152487
2012-03-10 07:37:27 +00:00
014e1cde5f
Fix the x86 disassembler to at least print the lock prefix if it is the first
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prefix. Added a FIXME to remind us this still does not work when it is not the
first prefix.
llvm-svn: 152414
2012-03-09 17:52:49 +00:00
520eb3ba8a
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
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llvm-svn: 152127
2012-03-06 18:33:12 +00:00
f0269b4270
Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
...
runs into the undefined 15 condition code value.
llvm-svn: 151844
2012-03-01 22:13:02 +00:00
6491c8020e
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
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llvm-svn: 151510
2012-02-27 01:54:29 +00:00
66a3597a4a
Add vmfunc instruction to X86 assembler and disassembler.
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llvm-svn: 150899
2012-02-19 01:39:49 +00:00
ed7aa46366
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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llvm-svn: 150873
2012-02-18 08:19:49 +00:00
924f9a671d
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
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Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
llvm-svn: 150664
2012-02-16 06:28:33 +00:00
d9ba4fd48f
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
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llvm-svn: 150169
2012-02-09 10:56:31 +00:00
2ba766ae84
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
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llvm-svn: 147368
2011-12-30 06:23:39 +00:00
03a0beda88
Add FMA4 instructions to disassembler.
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llvm-svn: 147367
2011-12-30 05:20:36 +00:00
d773607eee
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
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llvm-svn: 147353
2011-12-29 20:43:40 +00:00
8cab06a214
Expose FMA3 instructions to the disassembler.
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llvm-svn: 147351
2011-12-29 20:03:14 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
97b3da5433
Add several new instructions supported by the latest MicroBlaze.
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These instructions are not generated by the backend yet, this will come in a later commit.
llvm-svn: 145161
2011-11-27 05:16:58 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
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llvm-svn: 144683
2011-11-15 19:55:00 +00:00
3e2c6f380c
ARM VLDR/VSTR instructions don't need a size suffix.
...
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
69d57cf9c4
Simplify some uses of utohexstr.
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As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
fbb704f551
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
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llvm-svn: 143557
2011-11-02 18:03:14 +00:00
69e54a740c
Fix disassembly of some VST1 instructions.
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llvm-svn: 143507
2011-11-01 22:18:13 +00:00
40703f4252
More not-crashing NEON disassembly updates for the vld refactoring.
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llvm-svn: 143351
2011-10-31 17:17:32 +00:00
5524ce7d82
Fix illegal disassembly testcase.
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llvm-svn: 143231
2011-10-28 21:45:09 +00:00
dde461c8b1
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
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llvm-svn: 143208
2011-10-28 18:02:13 +00:00
f211416dde
Add testcase for r143162.
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llvm-svn: 143163
2011-10-27 22:54:14 +00:00
295b1e84ce
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
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llvm-svn: 142817
2011-10-24 18:04:29 +00:00
b05d9e9bea
Add X86 SARX, SHRX, and SHLX instructions.
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llvm-svn: 142779
2011-10-23 22:18:24 +00:00
980d59832a
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
e94d277db8
Add X86 MULX instruction for disassembler.
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llvm-svn: 142738
2011-10-23 00:33:32 +00:00
16c8fc5191
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
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llvm-svn: 142626
2011-10-20 22:23:58 +00:00
608c60c773
Fix decoding tests for fixed MSR encodings.
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llvm-svn: 142624
2011-10-20 22:01:48 +00:00
ef309c3384
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
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llvm-svn: 142480
2011-10-19 07:48:35 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
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llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
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llvm-svn: 142117
2011-10-16 07:05:40 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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llvm-svn: 142105
2011-10-16 03:51:13 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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llvm-svn: 142082
2011-10-15 20:46:47 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
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llvm-svn: 141947
2011-10-14 07:06:56 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141939
2011-10-14 03:21:46 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
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http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141854
2011-10-13 07:09:14 +00:00
Tim Northover