Commit Graph

997 Commits

Author SHA1 Message Date
Tom Stellard 2204137df9 R600: Add macro defs for all supported OpenCL extensions
llvm-svn: 242523
2015-07-17 13:16:52 +00:00
Tamas Berghammer 15ef947549 Fix android build after r242514
On android std::to_string isn't supported. Replace it with
llvm::utostr.

llvm-svn: 242516
2015-07-17 10:16:11 +00:00
Alexandros Lamprineas 65bc306345 -Refactored ARMTargetInfo in order to use the API of TargetParser
for extracting target specific information.
-Patches commit r241343: case 'armv7l' was unhandled in
 ARMTargetInfo::getCPUAttr(), and thus it was returning invalid
 characters for macro definition.

Change-Id: I1a0972e5ff5529cd17376c6562047bab8b4da32c
Phabricator: http://reviews.llvm.org/D10839
llvm-svn: 242514
2015-07-17 09:08:37 +00:00
Matthias Braun d1e2fad2e0 Allow __builtin_setjmp/__builtin_longjmp on ARM
The problems in the llvm target got fixed in r242481 and r242482.

Related to rdar://20544153, rdar://20660786

llvm-svn: 242489
2015-07-17 00:15:22 +00:00
David Majnemer c19475a8c9 [Targets] Define __BOOL_DEFINED for Windows targets in C++ mode
MSVC 4.2 didn't have bool as a builtin type but MSVC 5.0 does.  When
they added it, they added a macro (__BOOL_DEFINED) which allows build
scripts and the like to know if they should provide their own bool.

Clang always supports bool as a builtin type in C++ mode.

llvm-svn: 242307
2015-07-15 17:32:34 +00:00
Yaron Keren 321249cb2c Add support for armv7-windows-gnu targets to the clang front end.
http://reviews.llvm.org/D11071

Patch by Martell Malone
Reviewed by Reid Kleckner

llvm-svn: 242292
2015-07-15 13:32:23 +00:00
Paul Robinson d30e2eefc3 Add a "maximum TLS alignment" characteristic to the target info, so it
can be different from the normal variable maximum.
Add an error diagnostic for when TLS variables exceed maximum TLS alignment.
Currenty only PS4 sets an explicit maximum TLS alignment.

Patch by Charles Li!

llvm-svn: 242198
2015-07-14 20:52:32 +00:00
Eric Christopher e6b7cf4787 Fix a couple of typos: specifc->specific.
llvm-svn: 241924
2015-07-10 18:25:52 +00:00
Nemanja Ivanovic 26c3534b84 Add missing builtins to altivec.h for ABI compliance (vol. 3)
This patch corresponds to review:
http://reviews.llvm.org/D10972

Fix for the handling of dependent features that are enabled by default
on some CPU's (such as -mvsx, -mpower8-vector).

Also provides a number of new interfaces or fixes existing ones in
altivec.h.

Changed signatures to conform to ABI:
vector short vec_perm(vector signed short, vector signed short, vector unsigned char)
vector int vec_perm(vector signed int, vector signed int, vector unsigned char)
vector long long vec_perm(vector signed long long, vector signed long long, vector unsigned char)
vector signed char vec_sld(vector signed char, vector signed char, const int)
vector unsigned char vec_sld(vector unsigned char, vector unsigned char, const int)
vector bool char vec_sld(vector bool char, vector bool char, const int)
vector unsigned short vec_sld(vector unsigned short, vector unsigned short, const int)
vector signed short vec_sld(vector signed short, vector signed short, const int)
vector signed int vec_sld(vector signed int, vector signed int, const int)
vector unsigned int vec_sld(vector unsigned int, vector unsigned int, const int)
vector float vec_sld(vector float, vector float, const int)
vector signed char vec_splat(vector signed char, const int)
vector unsigned char vec_splat(vector unsigned char, const int)
vector bool char vec_splat(vector bool char, const int)
vector signed short vec_splat(vector signed short, const int)
vector unsigned short vec_splat(vector unsigned short, const int)
vector bool short vec_splat(vector bool short, const int)
vector pixel vec_splat(vector pixel, const int)
vector signed int vec_splat(vector signed int, const int)
vector unsigned int vec_splat(vector unsigned int, const int)
vector bool int vec_splat(vector bool int, const int)
vector float vec_splat(vector float, const int)

Added a VSX path to:
vector float vec_round(vector float)

Added interfaces:
vector signed char vec_eqv(vector signed char, vector signed char)
vector signed char vec_eqv(vector bool char, vector signed char)
vector signed char vec_eqv(vector signed char, vector bool char)
vector unsigned char vec_eqv(vector unsigned char, vector unsigned char)
vector unsigned char vec_eqv(vector bool char, vector unsigned char)
vector unsigned char vec_eqv(vector unsigned char, vector bool char)
vector signed short vec_eqv(vector signed short, vector signed short)
vector signed short vec_eqv(vector bool short, vector signed short)
vector signed short vec_eqv(vector signed short, vector bool short)
vector unsigned short vec_eqv(vector unsigned short, vector unsigned short)
vector unsigned short vec_eqv(vector bool short, vector unsigned short)
vector unsigned short vec_eqv(vector unsigned short, vector bool short)
vector signed int vec_eqv(vector signed int, vector signed int)
vector signed int vec_eqv(vector bool int, vector signed int)
vector signed int vec_eqv(vector signed int, vector bool int)
vector unsigned int vec_eqv(vector unsigned int, vector unsigned int)
vector unsigned int vec_eqv(vector bool int, vector unsigned int)
vector unsigned int vec_eqv(vector unsigned int, vector bool int)
vector signed long long vec_eqv(vector signed long long, vector signed long long)
vector signed long long vec_eqv(vector bool long long, vector signed long long)
vector signed long long vec_eqv(vector signed long long, vector bool long long)
vector unsigned long long vec_eqv(vector unsigned long long, vector unsigned long long)
vector unsigned long long vec_eqv(vector bool long long, vector unsigned long long)
vector unsigned long long vec_eqv(vector unsigned long long, vector bool long long)
vector float vec_eqv(vector float, vector float)
vector float vec_eqv(vector bool int, vector float)
vector float vec_eqv(vector float, vector bool int)
vector double vec_eqv(vector double, vector double)
vector double vec_eqv(vector bool long long, vector double)
vector double vec_eqv(vector double, vector bool long long)
vector bool long long vec_perm(vector bool long long, vector bool long long, vector unsigned char)
vector double vec_round(vector double)
vector double vec_splat(vector double, const int)
vector bool long long vec_splat(vector bool long long, const int)
vector signed long long vec_splat(vector signed long long, const int)
vector unsigned long long vec_splat(vector unsigned long long,
vector bool int vec_sld(vector bool int, vector bool int, const int)
vector bool short vec_sld(vector bool short, vector bool short, const int)

llvm-svn: 241904
2015-07-10 13:11:34 +00:00
Petar Jovanovic 26a4a40137 [MIPS] Add support for direct-to-nacl in Clang
For Mips direct-to-nacl, the goal is to be close to le32 front-end and
use Mips32EL backend. This patch defines new NaClMips32ELTargetInfo and
modifies it slightly to be close to le32. It also adds necessary parts,
inline with ARM and X86.

Differential Revision: http://reviews.llvm.org/D10739

llvm-svn: 241678
2015-07-08 13:07:31 +00:00
Renato Golin 15b86155c9 Revert "Refactored ARMTargetInfo in order to use the API of llvm/lib/Support/TargetParser.cpp
This reverts commit r241343, as it was, again, breaking all ARM buildbots.

llvm-svn: 241362
2015-07-03 16:41:13 +00:00
Alexandros Lamprineas eb73228888 - Refactored ARMTargetInfo in order to use the API of llvm/lib/Support/TargetParser.cpp
for extracting target specific information.
- Patch for commit 241267: ShouldUseInlineAtomic was set incorrectly when subArch was
  not specified, causing regressions.

Change-Id: Iabb35d59722f4972f1a3ab4365880add5bbcfdcc
llvm-svn: 241343
2015-07-03 11:57:23 +00:00
Rafael Espindola 5ab8e2e85c Revert "Refactored ARMTargetInfo in order to use the API of llvm/lib/Support/TargetParser.cpp for extracting target specific information."
This reverts commit r241267. Tests were failing on the bots.

llvm-svn: 241275
2015-07-02 15:14:10 +00:00
Alexandros Lamprineas ec44b157f1 Refactored ARMTargetInfo in order to use the API of llvm/lib/Support/TargetParser.cpp
for extracting target specific information.

Change-Id: Ia0b83ecdb8d9223f9c4ef38dd9206969f78e53f3
llvm-svn: 241267
2015-07-02 14:21:40 +00:00
Alexandros Lamprineas 73b076159b test commit
Change-Id: Ibaa2e1115544ddfa491335b81226819fd9cc04b4
llvm-svn: 241260
2015-07-02 13:21:34 +00:00
Alexey Bataev 0039651304 [OPENMP] Introduced type trait "__builtin_omp_required_simd_align" for default simd alignment.
Adds type trait "__builtin_omp_required_simd_align" after discussions here http://reviews.llvm.org/D9894
Differential Revision: http://reviews.llvm.org/D10597

llvm-svn: 241237
2015-07-02 03:40:19 +00:00
Eric Christopher 298ac300b2 Fix sse4 for target attribute feature additions.
This reinstates part of the hack removed in r233223, by special
casing sse4 as part of the feature additions. The notable change
here is that we consider it only as part of setting the SSE level
and not as part of the actual target features set which handles
setting the rest of the masks.

llvm-svn: 241130
2015-07-01 00:08:32 +00:00
Eric Christopher d983270976 Add support for the x86 builtin __builtin_cpu_supports.
This matches the implementation of the gcc support for the same
feature, including checking the values set up by libgcc at runtime.
The structure looks like this:

  unsigned int __cpu_vendor;
  unsigned int __cpu_type;
  unsigned int __cpu_subtype;
  unsigned int __cpu_features[1];

with a set of enums to match various fields that are field out after
parsing the output of the cpuid instruction.
This also adds a set of errors checking for valid input (and cpu).

compiler-rt support for this and the other builtins in this family
(__builtin_cpu_init and __builtin_cpu_is) are forthcoming.

llvm-svn: 240994
2015-06-29 21:00:05 +00:00
Ranjeet Singh ac08e53f3a [ARM] The bits set in the variable HW_FP could get unset
when iterating through the Features vector if we don't
keep track of what's already been set. This could lead to
the macro __ARM_FP getting the wrong value. This patch
fixes this issue by keeping track of the bits that have
already been set in the loop.

Differential Revision: http://reviews.llvm.org/D10395

llvm-svn: 240607
2015-06-24 23:39:25 +00:00
Ahmed Bougacha 0b938284da [CodeGen] Teach X86_64ABIInfo about AVX512.
As specified in the SysV AVX512 ABI drafts. It follows the same scheme
as AVX2: 

    Arguments of type __m512 are split into eight eightbyte chunks.
    The least significant one belongs to class SSE and all the others
    to class SSEUP.

This also means we change the OpenMP SIMD default alignment on AVX512.

Based on r240337.
Differential Revision: http://reviews.llvm.org/D9894

llvm-svn: 240338
2015-06-22 21:31:43 +00:00
Matt Arsenault 3ea39f9e78 AMDGPU: Fix places missed in rename
llvm-svn: 240148
2015-06-19 17:54:10 +00:00
Tom Stellard 64e0dd0a27 AMDGPU: Add missing GK_VOLCANIC_ISLANDS to switch statement
This fixes buildbot failures introduced by r240038.

llvm-svn: 240059
2015-06-18 21:13:29 +00:00
Tom Stellard 5c38440b2b R600: Add Volcanic Islands targets
Reviewers: arsenm

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D10316

llvm-svn: 240038
2015-06-18 19:14:15 +00:00
Ulrich Weigand 47fd253f56 [SystemZ] Mangle long double as __float128
In r239421, the mangling of long double on PowerPC Linux targets
was changed to use "g" instead of "e".  This same change also needs
to be done for SystemZ (all targets, since we support only Linux
on SystemZ anyway).

This is because an old ABI variant set "long double" to a 64-bit
type equivalent to "double", and the "e" mangling code is still
used to refer to that old ABI for compatibility reasons.

llvm-svn: 239822
2015-06-16 15:21:47 +00:00
Ed Schouten 7893e6874d Add some basic support for CloudABI on i686.
Some people want to experiment with building i686 CloudABI binaries. I
am not entirely sure this is a good idea, as I'd rather see Intel x32
support appear.

As it only requires a two-line change, let's at least provide compiler
to ease experimenting.

llvm-svn: 239689
2015-06-13 21:33:49 +00:00
Alexei Starovoitov f657ca8d78 [bpf] add support for BPF backend
add support for bpfel/bpfeb targets

llvm-svn: 239496
2015-06-10 22:59:13 +00:00
David Majnemer 2617ea6756 [ItaniumMangle] Mangle long double as __float128 for some Power targets
GCC mangles long double like __float128 in order to support
compatibility with ABI variants which had a different interpretation of
long double.

This fixes PR23791.

llvm-svn: 239421
2015-06-09 18:05:33 +00:00
Artyom Skrobov 902ac2d837 Simplify ARMTargetParser::parseArch(ARMTargetParser::getCanonical()), following r239099
Reviewers: rengolin

Reviewed By: rengolin

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D10256

llvm-svn: 239101
2015-06-04 21:31:41 +00:00
James Y Knight 4b4d19ede2 [SPARC] Fix types of size_t, intptr_t, and ptrdiff_t on Linux.
They should be 'int' instead of 'long int' everywhere else except
NetBSD too, from what I gather in GCC's spec files. So, optimistically
changing it for everyone else, too.

llvm-svn: 239046
2015-06-04 15:36:29 +00:00
David Majnemer 5c2589a50b [Basic] Transition getEnvironmentVersion from getOSVersion for android
'android' occupies the environment component of the triple.  Let's use
getEnvironmentVersion to extract it instead of getOSVersion.

llvm-svn: 238797
2015-06-01 23:38:25 +00:00
Tim Northover a8c168db7f ARM: fix ACLE predefine for iOS's "-arch armv7s".
We were getting "#define __ARM_ARCH_7 -S__ 1" which is really not a good idea.

llvm-svn: 238614
2015-05-29 21:28:25 +00:00
Renato Golin 391544c431 [ARMTargetParser] Removing string parsing from getCPUDefineSuffix. NFC.
Yet another FIXME from ARMTargetParser.

llvm-svn: 238416
2015-05-28 12:11:11 +00:00
David Majnemer ae1ed0edfe [Basic] Define __declspec for cygwin
Cygwin (and MinGW) targets define __declspec to __attribute__ unless
-fms-extensions is specified.  It turns out that cygwin headers rely on
the existence of this macro.

llvm-svn: 238394
2015-05-28 04:36:18 +00:00
Renato Golin f05bf0090b ARMTargetParser FIXME getCPUProfile A/R/M
This is the last of the easy ones.

llvm-svn: 238324
2015-05-27 14:15:12 +00:00
Renato Golin f5c4dec750 ARMTargetParser FIXME: ARMv8 detection for hdiv
Avoiding ugly combination of string parsing in the front-end. We still
need to move away from CPU parsing at all, but that's for a different
commit.

llvm-svn: 238318
2015-05-27 13:33:00 +00:00
Bill Schmidt 41e14c4dfa [PPC64] Add vector pack/unpack support from ISA 2.07
This patch adds support for the following new instructions in the
Power ISA 2.07:

  vpksdss
  vpksdus
  vpkudus
  vpkudum
  vupkhsw
  vupklsw

These instructions are available through the vec_packs, vec_packsu,
vec_unpackh, and vec_unpackl built-in interfaces.  These are
lane-sensitive instructions, so the built-ins have different
implementations for big- and little-endian, and the instructions must
be marked as killing the vector swap optimization for now.

The first three instructions perform saturating pack operations.  The
fourth performs a modulo pack operation, which means it can be
represented with a vector shuffle, and conversely the appropriate
vector shuffles may cause this instruction to be generated.  The other
instructions are only generated via built-in support for now.

I noticed during patch preparation that the macro __VSX__ was not
previously predefined when the power8-vector or direct-move features
are requested.  This is an error, and I've corrected that here as
well.

Appropriate tests have been added.

There is a companion patch to llvm for the rest of this support.

llvm-svn: 237500
2015-05-16 01:02:25 +00:00
Nemanja Ivanovic e97e111af4 Testing for the fix for bug 23429.
Follow-up to commit for revision 236848.
Just a test case for the macro definition under the right CPU/Arch.
One combination was actually missed in the initial fix:
  - powerpc64-unknown-unknown -mcpu=pwr8 (rather than -mcpu=power8).

llvm-svn: 237386
2015-05-14 20:02:24 +00:00
Vladimir Sukharev 85a19e92d7 [ARM] Fix of architecture naming typo
Inspired by James Greenhalgh's catch

Subscribers: cfe-commits

Relates to: http://reviews.llvm.org/rL237349

llvm-svn: 237370
2015-05-14 16:39:01 +00:00
Vladimir Sukharev c6dab75bd4 [ARM] Add v8.1a architecture
Add support for ARMv8.1a architecture. 

Briefly it is described on http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development

Reviewers: 	jmolloy, rengolin

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D8799

llvm-svn: 237349
2015-05-14 08:25:18 +00:00
Douglas Katzman 78d7c54f7c clang-format AllocateTarget. NFC
llvm-svn: 237183
2015-05-12 21:18:10 +00:00
Eric Christopher 9e172d20f0 Remove the code that pulled soft float attributes out of the feature
strings and remove the setting of TargetOptions::UseSoftFloat to
match the code change in llvm r237079.

llvm-svn: 237080
2015-05-12 01:26:21 +00:00
Eric Christopher 5eaf3815c0 Update initialization of a class variable and comment.
llvm-svn: 237071
2015-05-12 00:04:20 +00:00
Douglas Katzman f36dddf426 [Sparc] Add support for 'sparcel' to clang.
Differential Revision: http://reviews.llvm.org/D8784

llvm-svn: 237001
2015-05-11 15:21:44 +00:00
David Majnemer b710a938d6 Give isCompatibleWithMSVC a better interface
We now use an enum which maps the marketing name (almost always a year)
to the major version number.

llvm-svn: 236967
2015-05-11 03:57:49 +00:00
Nemanja Ivanovic 531a656cf0 Fix for bug 23429.
The macros for gcc atomic compare and swaps are defined for Power8 CPU's since
the functionality is provided in the back end.

llvm-svn: 236848
2015-05-08 13:07:48 +00:00
Reid Kleckner d167d42888 [AArch64] Advertise that the __sync_*_compare_and_swap_1/2/4/8 builtins work
Fixes PR23428, where std::thread in libstdc++ would go haywire without
these defines.

llvm-svn: 236605
2015-05-06 15:31:46 +00:00
Ulrich Weigand 66ff51b4ea [SystemZ] Add support for z13 and its vector facility
This patch adds support for the z13 architecture type.  For compatibility
with GCC, a pair of options -mvx / -mno-vx can be used to selectively
enable/disable use of the vector facility.

When the vector facility is present, we default to the new vector ABI.
This is characterized by two major differences:
- Vector types are passed/returned in vector registers
  (except for unnamed arguments of a variable-argument list function).
- Vector types are at most 8-byte aligned.

The reason for the choice of 8-byte vector alignment is that the hardware
is able to efficiently load vectors at 8-byte alignment, and the ABI only
guarantees 8-byte alignment of the stack pointer, so requiring any higher
alignment for vectors would require dynamic stack re-alignment code.

However, for compatibility with old code that may use vector types, when
*not* using the vector facility, the old alignment rules (vector types
are naturally aligned) remain in use.

These alignment rules are not only implemented at the C language level,
but also at the LLVM IR level.  This is done by selecting a different
DataLayout string depending on whether the vector ABI is in effect or not.

Based on a patch by Richard Sandiford.

llvm-svn: 236531
2015-05-05 19:35:52 +00:00
Jan Vesely eebeaea0ab R600: Add fma and ldexp asic specific feature macros
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 236453
2015-05-04 19:53:36 +00:00
Tim Northover f9b517c159 ARM: merge Cyclone into other ARMv8 CPUs and add tests for features.
Cyclone actually supports all the goodies you'd expect to come with an AArch64
CPU, so it doesn't need its own clause. Also we should probably be testing
these clauses.

llvm-svn: 236349
2015-05-01 21:17:25 +00:00
Jan Vesely a3abd6da8b R600: Report fp64 on all capable asics
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 236325
2015-05-01 17:38:13 +00:00