Don't chane the CFI information when a conditional instruction
is emulated (eg.: popeq {r0, pc}) because the CFI for the next
instruction should be the same as the CFI for the current instruction.
Differential revision: http://reviews.llvm.org/D11258
llvm-svn: 242519
* Add and fix the emulation of several instruction.
* Disable frame pointer usage on Android.
* Specify return address register for the unwind plan instead of explict
tracking the value of RA.
* Replace prologue detection heuristics (unreliable in several cases)
with a logic to follow the branch instructions and restore the CFI
value based on them. The target address for a branch should have the
same CFI as the source address (if they are in the same function).
* Handle symbols in ELF files where the symbol size is not specified
with calcualting their size based on the next symbol (already done
in MachO files).
* Fix architecture in FuncUnwinders with filling up the inforamtion
missing from the object file with the architecture of the target.
* Add code to read register wehn the value is set to "IsSame" as it
meanse the value of a register in the parent frame is the same as the
value in the current frame.
Differential revision: http://reviews.llvm.org/D10447
llvm-svn: 240533
The condition detection code is calculating the result of the condition
based on the first 3 bit of the condition and then negate it if the LSB
of the condition is set. It works for the normal conditions but 0b1110
and 0b1111 are special as both of them should evaluate to true
independently the value of CPSR. This CL removes the negating logic from
those cases.
Differential revision: http://reviews.llvm.org/D9219
llvm-svn: 235715
In the previous ordering some "blx <label>" instruction was recognised
as "b #imm24" instructions causing a failure in the instruction
emulator.
Differential revision: http://reviews.llvm.org/D9218
llvm-svn: 235714
Write the new cpsr value into the cpsr register if the BL or the BLX
instruction change the instruction set on arm.
Differential revision: http://reviews.llvm.org/D9188
llvm-svn: 235585
Summary:
This change refactors UnwindPlan::Row to be able to store the fact that the CFA is value is set
by evaluating a dwarf expression (DW_CFA_def_cfa_expression). This is achieved by creating a new
class CFAValue and moving all CFA setting/getting code there. Note that code using the new
CFAValue::isDWARFExpression is not yet present and will be added in a follow-up patch. Therefore,
this patch should not change the functionality in any way.
Test Plan: Ran tests on Mac and Linux. No regressions detected.
Reviewers: jasonmolenda, clayborg
Subscribers: lldb-commits
Differential Revision: http://reviews.llvm.org/D7755
llvm-svn: 230210
Replace adhoc inline implementation of llvm::array_lengthof in favour of the
implementation in LLVM. This is simply a cleanup change, no functional change
intended.
llvm-svn: 211868
and EmulateInstructionARM::GetFramePointerDWARFRegisterNumber to recognize
the Apple arm convention (of using r7 for the frame pointer, regardless of
thumb or arm) even if the OS does not match Darwin/MacOSX/iOS. Also
corrects the behavior for thumb code on non-Apple platforms.
<rdar://problem/14661537>
llvm-svn: 198648
Previously, an opcode set via SetOpcode32 (for example) was later
extracted via GetData() as a byte sequence in host order rather than
target order.
Review: http://llvm-reviews.chandlerc.com/D1838
llvm-svn: 196808
<rdar://problem/13594769>
Main changes in this patch include:
- cleanup plug-in interface and use ConstStrings for plug-in names
- Modfiied the BSD Archive plug-in to be able to pick out the correct .o file when .a files contain multiple .o files with the same name by using the timestamp
- Modified SymbolFileDWARFDebugMap to properly verify the timestamp on .o files it loads to ensure we don't load updated .o files and cause problems when debugging
The plug-in interface changes:
Modified the lldb_private::PluginInterface class that all plug-ins inherit from:
Changed:
virtual const char * GetPluginName() = 0;
To:
virtual ConstString GetPluginName() = 0;
Removed:
virtual const char * GetShortPluginName() = 0;
- Fixed up all plug-in to adhere to the new interface and to return lldb_private::ConstString values for the plug-in names.
- Fixed all plug-ins to return simple names with no prefixes. Some plug-ins had prefixes and most ones didn't, so now they all don't have prefixed names, just simple names like "linux", "gdb-remote", etc.
llvm-svn: 181631
Full UnwindPlan is trying to do an impossible unwind; in that case
invalidate the Full UnwindPlan and replace it with the architecture
default unwind plan.
This is a scenario that happens occasionally with arm unwinds in
particular; the instruction analysis based full unwindplan can
mis-parse the functions and the stack walk stops prematurely. Now
we can do a simpleminded frame-chain walk to find the caller frame
and continue the unwind. It's not ideal but given the complicated
nature of analyzing the arm functions, and the lack of eh_frame
information on iOS, it is a distinct improvement and fixes some
long-standing problems with the unwinder on that platform.
This is fixing <rdar://problem/12091421>. I may re-use this
invalidate feature in the future if I can identify other cases where
the full unwindplan's unwind information is clearly incorrect.
This checkin also includes some cleanup for the volatile register
definition in the arm ABI plugin for <rdar://problem/10652166>
although work remains to be done for that bug.
llvm-svn: 166757
- no setting auto completion
- very manual and error prone way of getting/setting variables
- tons of code duplication
- useless instance names for processes, threads
Now settings can easily be defined like option values. The new settings makes use of the "OptionValue" classes so we can re-use the option value code that we use to set settings in command options. No more instances, just "does the right thing".
llvm-svn: 162366
a shared pointer to ease some memory management issues with a patch
I'm working on.
The main complication with using SPs for these objects is that most
methods that build up an UnwindPlan will construct a Row to a given
instruction point in a function, then add additional regsaves in
the next instruction point to that row and push it again. A little
care is needed to not mutate the previous instruction point's Row
once these are switched to being held behing shared pointers.
llvm-svn: 160214
Switch over to the "*-apple-macosx" for desktop and "*-apple-ios" for iOS triples.
Also make the selection process for auto selecting platforms based off of an arch much better.
llvm-svn: 156354
For EmulateInstructionARM::EmulatePUSH(), fix the logical branch for when pc is pushed to behave
like the other cases where:
context.SetRegisterToRegisterPlusOffset (reg_info, sp_reg, addr - sp);
is called to inform of the operation to set a register value to a memory location calculated from
a base register plus an offset.
llvm-svn: 152670
For the default case (illegal encoding type), just return false instead of break.
A8.6.84 LDRSH (register)
A8.6.309 VLD1 (single element to all lanes)
llvm-svn: 137699
instructions if they are conditional. Also fixed issues where the PC wasn't
getting bit zero stripped for ARM targets when a stack frame was thumb. We
now properly call through the GetOpcodeLoadAddress() functions to make sure
the addresses are properly stripped for any targets that may decorate up
their addresses.
We now don't pass the SIGSTOP signals along. We can revisit this soon, but
currently this was interfering with debugging some older ARM targets that
don't have vCont support in the GDB server.
llvm-svn: 134461
parse NOP instructions. I added the new table entries for the NOP for the
plain NOP, Yield, WFE, WFI, and SEV variants. Modified the opcode emulation
function EmulateInstructionARM::EmulateMOVRdSP(...) to notify us when it is
creating a frame. Also added an abtract way to detect the frame pointer
register for both the standard ARM ABI and for Darwin.
Fixed GDBRemoteRegisterContext::WriteAllRegisterValues(...) to correctly be
able to individually write register values back if case the 'G' packet is
not implemented or returns an error.
Modified the StopInfoMachException to "trace" stop reasons. On ARM we currently
use the BVR/BCR register pairs to say "stop when the PC is not equal to the
current PC value", and this results in a EXC_BREAKPOINT mach exception that
has 0x102 in the code.
Modified debugserver to create the short option string from long option
definitions to make sure it doesn't get out of date. The short option string
was missing many of the newer short option values due to a modification of
the long options defs, and not modifying the short option string.
llvm-svn: 131911
bool
Address::SetLoadAddress (lldb::addr_t load_addr, Target *target);
Added an == and != operator to RegisterValue.
Modified the ThreadPlanTracer to use RegisterValue objects to store the
register values when single stepping. Also modified the output to be a bit
less wide.
Fixed the ABIMacOSX_arm to not overwrite stuff on the stack. Also made the
trivial function call be able to set the ARM/Thumbness of the target
correctly, and also sets the return value ARM/Thumbness.
Fixed the encoding on the arm s0-s31 and d16 - d31 registers when the default
register set from a standard GDB server register sets.
llvm-svn: 131517
respective ABI plugins as they were plug-ins that supplied ABI specfic info.
Also hookep up the UnwindAssemblyInstEmulation so that it can generate the
unwind plans for ARM.
Changed the way ABI plug-ins are handed out when you get an instance from
the plug-in manager. They used to return pointers that would be mananged
individually by each client that requested them, but now they are handed out
as shared pointers since there is no state in the ABI objects, they can be
shared.
llvm-svn: 131193
into some cleanup I have been wanting to do when reading/writing registers.
Previously all RegisterContext subclasses would need to implement:
virtual bool
ReadRegisterBytes (uint32_t reg, DataExtractor &data);
virtual bool
WriteRegisterBytes (uint32_t reg, DataExtractor &data, uint32_t data_offset = 0);
There is now a new class specifically designed to hold register values:
lldb_private::RegisterValue
The new register context calls that subclasses must implement are:
virtual bool
ReadRegister (const RegisterInfo *reg_info, RegisterValue ®_value) = 0;
virtual bool
WriteRegister (const RegisterInfo *reg_info, const RegisterValue ®_value) = 0;
The RegisterValue class must be big enough to handle any register value. The
class contains an enumeration for the value type, and then a union for the
data value. Any integer/float values are stored directly in an appropriate
host integer/float. Anything bigger is stored in a byte buffer that has a length
and byte order. The RegisterValue class also knows how to copy register value
bytes into in a buffer with a specified byte order which can be used to write
the register value down into memory, and this does the right thing when not
all bytes from the register values are needed (getting a uint8 from a uint32
register value..).
All RegiterContext and other sources have been switched over to using the new
regiter value class.
llvm-svn: 131096
Tamas Berghammer