980d59832a
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
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llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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llvm-svn: 142105
2011-10-16 03:51:13 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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llvm-svn: 142082
2011-10-15 20:46:47 +00:00
60aa85b672
Tidy up a bit more, fix tab and remove trailing whitespaces
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llvm-svn: 140186
2011-09-20 21:45:26 +00:00
05f3f4939a
Tidy up code!
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llvm-svn: 140183
2011-09-20 21:39:06 +00:00
d126347f32
Re-write part of VEX encoding logic, to be more easy to read! Also fix
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a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
22241acc29
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
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implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
eda1d4f3ba
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
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This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
llvm-svn: 136292
2011-07-27 23:22:03 +00:00
6381c0100b
Explicitly cast narrowing conversions inside {}s that will become errors in
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C++0x.
llvm-svn: 136211
2011-07-27 06:22:51 +00:00
b25310095f
More refactoring.
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llvm-svn: 135939
2011-07-25 19:33:48 +00:00
Craig Topper