86c7b46680
AVX-512: Fixed a bug in extracting subvector from v64i1
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By Igor Breger (igor.breger@intel.com )
llvm-svn: 238322
2015-05-27 14:09:33 +00:00
3948c590e3
AVX-512: Implemented all forms of sign-extend and zero-extend instructions for KNL and SKX
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Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238301
2015-05-27 08:15:19 +00:00
f61727d880
AVX-512: fixed algorithm of building vectors of i1 elements
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fixed extract-insert i1 element,
load i1, zextload i1 should be with "and $1, %reg" to prevent loading garbage.
added a bunch of new tests.
llvm-svn: 237793
2015-05-20 14:32:03 +00:00
a8200603d4
AVX-512: fixed extended load to 512-bit register
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llvm-svn: 237537
2015-05-17 08:08:06 +00:00
d1084c5b3f
AVX-512: Extend/Truncate operations for SKX,
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SETCC for bit-vectors
llvm-svn: 235875
2015-04-27 12:57:59 +00:00
44bf0637d5
AVX-512-SKX: Added instruction VPMOVM2B/W/D/Q.
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This instruction allows to broadacst mask vector to data vector.
llvm-svn: 219083
2014-10-05 14:11:08 +00:00
34d2d76d25
AVX-512: Fixed a bug in emitting compare for MVT:i1 type.
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Added a test.
llvm-svn: 215889
2014-08-18 11:59:06 +00:00
2efed98b58
AVX-512: added a lit test for truncate operation
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llvm-svn: 201763
2014-02-20 07:34:13 +00:00
c10563d14e
Fix broken CHECK lines.
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llvm-svn: 199016
2014-01-11 21:06:00 +00:00
f404e054a1
AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD;
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Optimized a truncate pattern.
llvm-svn: 198562
2014-01-05 14:21:07 +00:00
8952974e29
AVX-512: implemented extractelement with variable index.
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Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.
llvm-svn: 190595
2013-09-12 08:55:00 +00:00
980c6b08b1
AVX-512: added extend and truncate instructions.
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llvm-svn: 189580
2013-08-29 11:56:53 +00:00
Elena Demikhovsky