Douglas Katzman
289ec857d2
[X86]: Correctly sign-extend 16-bit immediate in CALL instruction.
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Patch by Matthew Barney. Thanks!
Differential Revision: http://reviews.llvm.org/D9514
llvm-svn: 240795
2015-06-26 16:58:59 +00:00
Douglas Katzman
6dc1397298
[X86] Fix PR23271 - RIP-relative decoding bug in disassembler.
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Differential Revision: http://reviews.llvm.org/D9110
llvm-svn: 237310
2015-05-13 22:44:52 +00:00
Elena Demikhovsky
29792e9a80
AVX-512: Added all forms of FP compare instructions for KNL and SKX.
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Added intrinsics for the instructions. CC parameter of the intrinsics was changed from i8 to i32 according to the spec.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 236714
2015-05-07 11:24:42 +00:00
Rafael Espindola
dd3add6c60
Fix the operand encoding in the test instruction.
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Fixes pr22995.
llvm-svn: 233686
2015-03-31 12:31:55 +00:00
Craig Topper
09b27e7b24
[X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that doesn't fit in 5-bits. Fixes PR22743.
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llvm-svn: 230924
2015-03-02 00:22:29 +00:00
Craig Topper
8659344d93
[X86] Add some missing redundant MMX and SSE encodings for disassembler.
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llvm-svn: 230165
2015-02-22 07:50:41 +00:00
Craig Topper
916708f152
[X86] Add support for parsing and printing the mnemonic aliases for the XOP VPCOM instructions.
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llvm-svn: 229078
2015-02-13 07:42:25 +00:00
Craig Topper
1d472db8cc
[X86] Add GETSEC instruction.
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llvm-svn: 228514
2015-02-07 23:36:36 +00:00
Craig Topper
d193763f1c
[X86] Add assembler and disassembler test cases for clflushopt, clwb, pcommit, xsaves, xrstors, xsavec
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llvm-svn: 228385
2015-02-06 06:19:28 +00:00
Craig Topper
6b4499a393
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output.
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llvm-svn: 227963
2015-02-03 11:03:57 +00:00
Craig Topper
7d3c6d307a
[X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions.
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llvm-svn: 227302
2015-01-28 10:09:56 +00:00
Craig Topper
620b50cc23
[X86] Convert all the i8imm used by SSE and AVX instructions to u8imm.
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This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate.
llvm-svn: 226645
2015-01-21 08:15:54 +00:00
Craig Topper
7c10252943
[X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized.
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llvm-svn: 225432
2015-01-08 07:41:30 +00:00
Craig Topper
639445494f
[X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.
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Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building.
llvm-svn: 225256
2015-01-06 08:59:30 +00:00
Craig Topper
ae8e1b3831
[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present.
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llvm-svn: 225099
2015-01-03 00:00:20 +00:00
Craig Topper
055845f5cb
[X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates.
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This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used.
Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction.
llvm-svn: 225075
2015-01-02 07:02:25 +00:00
Craig Topper
a7a8c4c09e
[X86] Update disassembler tests for absolute move instructions to check the encodings. This provides testing for r225036. 64-bit mode is still broken.
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llvm-svn: 225037
2014-12-31 07:24:23 +00:00
Craig Topper
aa1c51ee01
Testcases for r224939.
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llvm-svn: 224976
2014-12-30 02:35:56 +00:00
Craig Topper
c4b12166f2
[X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them.
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llvm-svn: 224862
2014-12-26 18:20:05 +00:00
Craig Topper
d5b39237a1
[X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix to not fail to disassembler CR9-CR15 references.
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llvm-svn: 224861
2014-12-26 18:19:44 +00:00
Craig Topper
ee9eef2fd8
Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4.
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llvm-svn: 224846
2014-12-26 06:36:28 +00:00
Elena Demikhovsky
4b01b7306c
AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instruction
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llvm-svn: 220638
2014-10-26 09:52:24 +00:00
Craig Topper
0676b902ad
[X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit mode for certain instructions it shouldn't.
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Unfortunately, this isn't easy to fix since there's no simple way to figure out from the disassembler tables whether the W-bit is being used to select a 64-bit GPR or if its a required part of the opcode. The fix implemented here just looks for "64" in the instruction name and ignores the W-bit in 32-bit mode if its present.
Fixes PR21169.
llvm-svn: 219194
2014-10-07 07:29:50 +00:00
Adam Nemet
5933c2f824
[X86] AVX512: Add disassembler support for compressed displacement
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There are two parts here. First is to modify tablegen to adjust the encoding
type ENCODING_RM with the scaling factor.
The second is to use the new encoding types to compute the correct
displacement in the decoder.
Fixes <rdar://problem/17608489>
llvm-svn: 213281
2014-07-17 17:04:56 +00:00
Adam Nemet
8ae70506ea
[Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields
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V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and
NDS register fields. This was simply not used in the decoder until now.
Fixes <rdar://problem/17402661>
llvm-svn: 211565
2014-06-24 01:42:32 +00:00
Jim Grosbach
3fdf7cfba0
llvm-mc: Add option for prefering hex format disassembly.
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Previously there was a separate mode entirely (--hdis vs.
--disassemble). It makes a bit more sense for the immediate printing
style to be a flag for --disassmeble rather than an entirely different
thing.
llvm-svn: 210700
2014-06-11 20:26:40 +00:00
Alp Toker
d3d017cf00
Reduce verbiage of lit.local.cfg files
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We can just split targets_to_build in one place and make it immutable.
llvm-svn: 210496
2014-06-09 22:42:55 +00:00
Elena Demikhovsky
8ac0bf96f0
X86Disassembler - fixed a bug in immediate print
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llvm-svn: 206953
2014-04-23 07:21:04 +00:00
Craig Topper
0a9bf4c0c5
[X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm.
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llvm-svn: 206447
2014-04-17 06:33:45 +00:00
Craig Topper
ccb38c5588
Test case for r204305.
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llvm-svn: 204316
2014-03-20 06:45:10 +00:00
Craig Topper
0d1fd55c13
Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
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llvm-svn: 201641
2014-02-19 05:34:21 +00:00
Craig Topper
fae5ac27a2
Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.
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llvm-svn: 201507
2014-02-17 10:03:43 +00:00
Craig Topper
34875ab0b5
Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.
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llvm-svn: 201463
2014-02-15 07:29:18 +00:00
David Woodhouse
caaa2850c0
[x86] Fix disassembly of MOV16ao16 et al.
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The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.
llvm-svn: 199654
2014-01-20 12:02:53 +00:00
David Woodhouse
9c74fdb8b9
[x86] Fix 16-bit disassembly of JCXZ/JECXZ
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llvm-svn: 199653
2014-01-20 12:02:48 +00:00
David Woodhouse
3442f3429e
[x86] Rename MOVSD/STOSD/LODSD/OUTSD to MOVSL/STOSL/LODSL/OUTSL
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The disassembler has a special case for 'L' vs. 'W' in its heuristic for
checking for 32-bit and 16-bit equivalents. We could expand the heuristic,
but better just to be consistent in using the 'L' suffix.
llvm-svn: 199652
2014-01-20 12:02:44 +00:00
David Woodhouse
70ced3e0b2
[x86] Fix disassembly of callw instruction
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Not quite sure why this was marked isAsmParserOnly, but it means that the
disassembler can't see it either.
llvm-svn: 199651
2014-01-20 12:02:40 +00:00
David Woodhouse
5cf4c6750d
[x86] Fix 16-bit handling of OpSize bit
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When disassembling in 16-bit mode the meaning of the OpSize bit is
inverted. Instructions found in the IC_OPSIZE context will actually
*not* have the 0x66 prefix, and instructions in the IC context will
have the 0x66 prefix. Make use of the existing special-case handling
for the 0x66 prefix being in the wrong place, to cope with this.
llvm-svn: 199650
2014-01-20 12:02:35 +00:00
Craig Topper
35da3d190a
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
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llvm-svn: 199364
2014-01-16 07:36:58 +00:00
Craig Topper
9155118602
Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
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llvm-svn: 198278
2014-01-01 15:29:32 +00:00
Craig Topper
3fec8c612e
Add two fp test cases I missed in my previous commit.
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llvm-svn: 198269
2013-12-31 23:15:19 +00:00
Craig Topper
719560102d
Add more X86 FP stack disassembler test cases.
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llvm-svn: 198268
2013-12-31 22:51:53 +00:00
Craig Topper
e98c8cb9f0
Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
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llvm-svn: 198265
2013-12-31 17:21:44 +00:00
Elena Demikhovsky
371e363833
AVX-512: decoder for AVX-512, made by Alexey Bader.
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llvm-svn: 198013
2013-12-25 11:40:51 +00:00
Craig Topper
4432208884
Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
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llvm-svn: 192566
2013-10-14 01:42:32 +00:00
Craig Topper
72c8cd7bc3
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
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llvm-svn: 192171
2013-10-08 05:53:50 +00:00
Craig Topper
07ad1b23bb
Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
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llvm-svn: 192090
2013-10-07 07:19:47 +00:00
Craig Topper
2658d89728
Add disassembler support for long encodings for INC/DEC in 32-bit mode.
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llvm-svn: 192086
2013-10-07 04:28:06 +00:00
Craig Topper
9e3e38ae3f
Add XOP disassembler support. Fixes PR13933.
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llvm-svn: 191874
2013-10-03 05:17:48 +00:00
Craig Topper
93a3d5973d
Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits.
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llvm-svn: 191650
2013-09-30 02:50:51 +00:00