99c6c29c0c
Fixed MSVC Win64 warning of implicit conversion of 32-bit shift to 64-bits.
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llvm-svn: 258084
2016-01-18 21:11:19 +00:00
7aae9b3782
[Hexagon] Recognize more copy-equivalents in RDF optimizations
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llvm-svn: 258076
2016-01-18 20:45:51 +00:00
adc64b7df0
[RDF] Improvements to copy propagation
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- Allow any instruction to define equality between registers.
- Keep the DFG updated.
llvm-svn: 258075
2016-01-18 20:43:57 +00:00
e6b0662092
[RDF] Improve compile-time performance of dead code elimination
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llvm-svn: 258074
2016-01-18 20:42:47 +00:00
69e670d5f9
[RDF] Allow unlinking ref nodes from data-flow chains only
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llvm-svn: 258073
2016-01-18 20:41:34 +00:00
5f6eaac611
GlobalValue: use getValueType() instead of getType()->getPointerElementType().
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Reviewers: mjacob
Subscribers: jholewinski, arsenm, dsanders, dblaikie
Patch by Eduard Burtescu.
Differential Revision: http://reviews.llvm.org/D16260
llvm-svn: 257999
2016-01-16 20:30:46 +00:00
2a3b2f9841
[Hexagon] Generate CONST64 when optimizing for size in copy-to-combine
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llvm-svn: 257891
2016-01-15 14:08:31 +00:00
9b7320e621
[Hexagon] Handle DBG_VALUE instructions in copy-to-combine
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llvm-svn: 257890
2016-01-15 13:55:57 +00:00
0d11212f00
[Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword
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llvm-svn: 257815
2016-01-14 21:59:22 +00:00
5337a3e965
[Hexagon] Handle HVX registers in bit simplification
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llvm-svn: 257811
2016-01-14 21:45:43 +00:00
da00f2fdf4
Update to use new name alignTo().
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llvm-svn: 257804
2016-01-14 21:06:47 +00:00
237b96132d
[Hexagon] Expand pseudo instruction Insert4
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llvm-svn: 257771
2016-01-14 15:37:16 +00:00
b28ae10a16
[Hexagon] Handle branches with non-mbb operands
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llvm-svn: 257768
2016-01-14 15:05:27 +00:00
8340f94df1
Convert a few assert failures into proper errors.
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Fixes PR25944.
llvm-svn: 257697
2016-01-13 22:56:57 +00:00
a61f7da6ba
[Hexagon] Fix the options controlling jump table generation
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llvm-svn: 257679
2016-01-13 21:43:13 +00:00
a3c5d44437
[Hexagon] Do not insert non-phis before phis in bit simplification
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llvm-svn: 257606
2016-01-13 15:48:18 +00:00
f62d44be28
Replace inherited constructor with an explicit one
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Some bots failed when the inherited constructor was used.
llvm-svn: 257508
2016-01-12 19:27:59 +00:00
1279881315
[Hexagon] Implement RDF-based post-RA optimizations
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- Handle simple cases of register copies (what current RDF CP allows).
- Hexagon-specific dead code elimination: handles dead address updates
in post-increment instructions.
llvm-svn: 257504
2016-01-12 19:09:01 +00:00
c09d630e50
RDF: Copy propagation
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This is a very limited implementation of DFG-based copy propagation.
It only handles actual COPY instructions (does not handle other equivalents
such as add-immediate with a 0 operand).
The major limitation is that it does not update the DFG: that will be the
change required to make it more robust (hopefully coming up soon).
llvm-svn: 257490
2016-01-12 17:23:48 +00:00
6f4000e763
RDF: Dead code elimination
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Utility class to perform DFG-based dead code elimination.
llvm-svn: 257485
2016-01-12 17:01:16 +00:00
8dca45efa8
Fix compiler warnings from r257477
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llvm-svn: 257483
2016-01-12 16:51:55 +00:00
acdff46a9c
RDF: Implement register liveness analysis
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Compute block live-ins and operand kill flags from the DFG.
llvm-svn: 257480
2016-01-12 15:56:33 +00:00
b5b5a1d7ad
Register Data Flow: data flow graph
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Target independent, SSA-based data flow framework for representing
data flow between physical registers.
This commit implements the creation of the actual data flow graph.
llvm-svn: 257477
2016-01-12 15:09:49 +00:00
ab8cc02ba5
[Hexagon] Make helper function static. NFC.
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llvm-svn: 257476
2016-01-12 14:58:49 +00:00
bc17b68a47
[Hexagon] Add check for nullptr in getFixupNoBits
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llvm-svn: 257338
2016-01-11 15:51:53 +00:00
f49a8411f8
[Hexagon] Add implicit uses of GP to GP-relative loads and stores
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llvm-svn: 257337
2016-01-11 15:49:58 +00:00
b024445444
[Hexagon] Mark D14 and GP as reserved registers
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llvm-svn: 257336
2016-01-11 15:47:41 +00:00
ccd3bfc3c8
[Hexagon] Replace a static member variable in HexagonCVIResource (NFC)
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This creates one instance of TUL per HexagonShuffler, which avoids thread-safety
issues with future changes.
llvm-svn: 257215
2016-01-08 22:07:25 +00:00
2d0418e842
[Hexagon] Add system instructions for cache manipulation
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llvm-svn: 256936
2016-01-06 14:22:22 +00:00
fd2c6a3be0
[TableGen] Modify the AsmMatcherEmitter to only apply the table growth from r252440 to the Hexagon target.
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This restores the previous behavior of not including the mnemonic in the classes table for every target that starts instruction lines with the mnemonic. Not only did the table size increase by 1 entry, but the class enum increased in size which caused every class in the array to increase in size. It also grew the size of the function that parsers tokens into classes by a substantial amount.
This adds a new HasMnemonicFirst flag to all AsmParsers. It's set to 1 by default and Hexagon target overrides it to 0.
For the X86 target alone this recovers 324KB of size on the llvm-mc executable.
I believe the current state is still a bad design choice for the Hexagon target as it causes most of the parsing to do a linear search through the entire match table to comparing operands against every instruction until it finds one that works. At least for the other targets we do a binary search based on mnemonic over which to do the linear scan.
llvm-svn: 256669
2015-12-31 08:18:23 +00:00
21dc8bdd9e
[Hexagon] Add PIC support
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llvm-svn: 256025
2015-12-18 20:19:30 +00:00
4f9164d9b3
[Hexagon] Misc fixes to r255807
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llvm-svn: 255811
2015-12-16 20:07:04 +00:00
56bbf54b43
[Hexagon] Update the Hexagon packetizer
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llvm-svn: 255807
2015-12-16 19:36:12 +00:00
b51460cf86
[Hexagon] Make memcpy lowering thread-safe
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This removes an unpleasant hack involving a global variable for special
lowering of certain memcpy calls. These are now lowered as intended in
EmitTargetCodeForMemcpy in the same way that other targets do it.
llvm-svn: 255785
2015-12-16 17:29:37 +00:00
372bd80834
[Hexagon] Preprocess mapped instructions before lowering to MC
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llvm-svn: 255653
2015-12-15 17:05:45 +00:00
5e6f2bd0cb
[Hexagon] Add "const" to function parameters in HexagonInstrInfo
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llvm-svn: 255544
2015-12-14 21:32:25 +00:00
dac7102874
[Packetizer] Add AliasAnalysis as a parameter to the packetizer
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This will make the depedence graph more accurate if an alias analysis
is provided. If nullptr is specified in its place, the behavior will
remain as it is currently.
llvm-svn: 255540
2015-12-14 20:35:13 +00:00
d44a1fd506
Add "const" to function arguments in DFAPacketizer
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llvm-svn: 255526
2015-12-14 18:54:44 +00:00
759a7d0ed7
[Hexagon] Subtarget features/default CPU corrections
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llvm-svn: 255501
2015-12-14 15:03:54 +00:00
c106989fd5
Normalize MBB's successors' probabilities in several locations.
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This patch adds some missing calls to MBB::normalizeSuccProbs() in several
locations where it should be called. Those places are found by checking if the
sum of successors' probabilities is approximate one in MachineBlockPlacement
pass with some instrumented code (not in this patch).
Differential revision: http://reviews.llvm.org/D15259
llvm-svn: 255455
2015-12-13 09:26:17 +00:00
e6540e244a
[Hexagon] Add NewValueJump support for C4_cmpneq, C4_cmplte, C4_cmplteu
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llvm-svn: 255027
2015-12-08 16:28:32 +00:00
e4b9f507cf
fix 'the the '; NFC
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llvm-svn: 254928
2015-12-07 19:21:39 +00:00
15576e1c8f
Use make_range to reduce mentions of iterator type. NFC
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llvm-svn: 254872
2015-12-06 05:08:07 +00:00
5c32279bee
[Hexagon] Don't call getNumImplicitDefs and then iterate over the count. getNumImplicitDefs contains a loop so its better to just loop over the null terminated implicit def list. NFC
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llvm-svn: 254852
2015-12-05 17:34:07 +00:00
e5e035a3a8
Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.
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llvm-svn: 254843
2015-12-05 07:13:35 +00:00
f1b3e5e52e
[Hexagon] Simplify LowerCONCAT_VECTORS, handle different types better
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llvm-svn: 254724
2015-12-04 16:18:15 +00:00
4c606e66a7
[Hexagon] Using multiply instead of shift on signed number which can be UB
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llvm-svn: 254719
2015-12-04 15:48:45 +00:00
15ca65c253
[Hexagon] Adding shuffling resources for HVX instructions and tests for instruction encodings.
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llvm-svn: 254652
2015-12-03 21:44:28 +00:00
7709aa0e07
[Hexagon] Remove variable unused in NDEBUG build
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llvm-svn: 254623
2015-12-03 17:53:34 +00:00
c168c0165c
[Hexagon] Implement CONCAT_VECTORS for HVX using V6_vcombine
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llvm-svn: 254617
2015-12-03 16:47:20 +00:00
Simon Pilgrim