de98fae368
[Sparc] Add support for parsing synthetic instruction 'mov'.
...
llvm-svn: 200965
2014-02-07 09:06:52 +00:00
ced9226b0f
[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.
...
llvm-svn: 200963
2014-02-07 07:34:49 +00:00
fd07500dd1
[Sparc] Emit relocations for Thread Local Storage (TLS) when integrated assembler is used.
...
llvm-svn: 200962
2014-02-07 05:54:20 +00:00
104643d0aa
[Sparc] Emit correct relocations for PIC code when integrated assembler is used.
...
llvm-svn: 200961
2014-02-07 04:24:35 +00:00
dfe09b1b5b
[Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags.
...
llvm-svn: 200960
2014-02-07 02:36:06 +00:00
4998280fdf
Just returning false is the default.
...
llvm-svn: 200890
2014-02-06 00:03:15 +00:00
b4eec1daa1
Remove support for not using .loc directives.
...
Clang itself was not using this. The only way to access it was via llc.
llvm-svn: 200862
2014-02-05 18:00:21 +00:00
52b6473d74
[Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly.
...
llvm-svn: 200617
2014-02-01 18:54:16 +00:00
902d97bc8b
[Sparc] Save and restore float registers that may be used for parameter passing.
...
llvm-svn: 200509
2014-01-31 01:53:08 +00:00
ef1d59a175
Implement SPARCv9 atomic_swap_64 with a pseudo.
...
The SWAP instruction only exists in a 32-bit variant, but the 64-bit
atomic swap can be implemented in terms of CASX, like the other atomic
rmw primitives.
llvm-svn: 200453
2014-01-30 04:48:46 +00:00
141d0e2221
[Sparc] Use %r_disp32 for pc_rel entries in FDE as well.
...
This makes MCAsmInfo::getExprForFDESymbol() a virtual function and overrides it in SparcMCAsmInfo.
llvm-svn: 200376
2014-01-29 06:59:20 +00:00
fd5c1f9497
[Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame.
...
Otherwise, assembler (gas) fails to assemble them with error message "operation
combines symbols in different segments". This is because MC computes
pc_rel entries with subtract expression between labels from different sections.
llvm-svn: 200373
2014-01-29 04:51:35 +00:00
50f32d949b
[SparcV9] Use correct register class (I64RegClass) to hold the address of _GLOBAL_OFFSET_TABLE_ in sparcv9.
...
llvm-svn: 200368
2014-01-29 03:35:08 +00:00
a86694ca7a
[Sparc] Fix breakage in r200345
...
Oops. Don't do build tests on patches like that with --enable-targets=x86_64
llvm-svn: 200355
2014-01-28 23:38:16 +00:00
3fa98a65e9
Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()
...
llvm-svn: 200349
2014-01-28 23:13:18 +00:00
9784cef38d
Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()
...
llvm-svn: 200348
2014-01-28 23:13:07 +00:00
e6c13e4abd
Change MCStreamer EmitInstruction interface to take subtarget info
...
llvm-svn: 200345
2014-01-28 23:12:42 +00:00
83c677353b
Fix the DWARF EH encodings for Sparc PIC code.
...
Also emit the stubs that were generated for references to typeinfo
symbols.
llvm-svn: 200282
2014-01-28 02:52:26 +00:00
6f39ce4be2
Clean up the Legal/Expand logic for SPARC popc.
...
llvm-svn: 200141
2014-01-26 08:12:34 +00:00
e41383f899
Pass a MCSubtargetInfo down to the TargetStreamer creation.
...
With this the target streamers will be able to know the target features that
are in use.
llvm-svn: 200135
2014-01-26 06:38:58 +00:00
ead3b3d7a1
Only generate the popc instruction for SPARC CPUs that implement it.
...
The popc instruction is defined in the SPARCv9 instruction set
architecture, but it was emulated on CPUs older than Niagara 2.
llvm-svn: 200131
2014-01-26 06:09:59 +00:00
39f0833f47
Fix swapped CASA operands.
...
Found by SingleSource/UnitTests/AtomicOps.c
llvm-svn: 200130
2014-01-26 06:09:54 +00:00
24ea09ef7d
Construct the MCStreamer before constructing the MCTargetStreamer.
...
This has a few advantages:
* Only targets that use a MCTargetStreamer have to worry about it.
* There is never a MCTargetStreamer without a MCStreamer, so we can use a
reference.
* A MCTargetStreamer can talk to the MCStreamer in its constructor.
llvm-svn: 200129
2014-01-26 06:06:37 +00:00
cb40291100
Fix known typos
...
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.
llvm-svn: 200018
2014-01-24 17:20:08 +00:00
dc3bcc19cf
[SparcV9] Add support for JIT in Sparc64.
...
With this change, all supported tests in test/ExecutionEngine pass in sparcv9.
llvm-svn: 199977
2014-01-24 07:10:19 +00:00
05ae2d6715
Implement atomicrmw operations in 32 and 64 bits for SPARCv9.
...
These all use the compare-and-swap CASA/CASXA instructions.
llvm-svn: 199975
2014-01-24 06:23:31 +00:00
98aa7fab7e
[Sparc] Correct quad register list in the asm parser.
...
Add test cases to check parsing of v9 double registers and their aliased quad registers.
llvm-svn: 199974
2014-01-24 05:24:01 +00:00
7383d4a9c5
Fix out of bounds access to the double regs array. Given the
...
code this looks correct, but could use review. The previous
was definitely not correct.
llvm-svn: 199940
2014-01-23 21:41:10 +00:00
dd634cac74
[Sparc] Add support for inline assembly constraints which specify registers by their aliases.
...
llvm-svn: 199786
2014-01-22 03:18:42 +00:00
407e442245
[Sparc] Add support for inline assembly constraint 'I'.
...
llvm-svn: 199781
2014-01-22 01:29:51 +00:00
f52927fb1b
[Sparc] Do not add PC to _GLOBAL_OFFSET_TABLE_ address to access GOT in absolute code.
...
Fixes PR#18521
llvm-svn: 199775
2014-01-22 00:13:18 +00:00
06234ec147
Add FPExt option to CCValAssign::LocInfo. When generating calling-convention
...
promotion code, Tablegen will now select FPExt for floating point promotions
(previously it had returned AExt, which is not valid for floating point types).
Any out-of-tree targets that were relying on AExt being returned for FP
promotions will need to update their code check for FPExt instead.
llvm-svn: 199252
2014-01-14 19:56:36 +00:00
4a1a360634
Make getTargetStreamer return a possibly null pointer.
...
This will allow it to be called from target independent parts of the main
streamer that don't know if there is a registered target streamer or not. This
in turn will allow targets to perform extra actions at specified points in the
interface: add extra flags for some labels, extra work during finalization, etc.
llvm-svn: 199174
2014-01-14 01:21:46 +00:00
1995b9fead
Handle bundled terminators in isBlockOnlyReachableByFallthrough.
...
Targets like SPARC and MIPS have delay slots and normally bundle the
delay slot instruction with the corresponding terminator.
Teach isBlockOnlyReachableByFallthrough to find any MBB operands on
bundled terminators so SPARC doesn't need to specialize this function.
llvm-svn: 199061
2014-01-12 19:24:08 +00:00
cd4d9ac62a
[Sparc] Add support for parsing floating point instructions.
...
llvm-svn: 199033
2014-01-12 04:48:54 +00:00
0b9debf1f6
[Sparc] Replace (unsigned)-1 with ~OU as suggested by Reid Kleckner.
...
llvm-svn: 199031
2014-01-12 04:34:31 +00:00
e7084a1c5c
The SPARCv9 ABI returns a float in %f0.
...
This is different from the argument passing convention which puts the
first float argument in %f1.
With this patch, all returned floats are treated as if the 'inreg' flag
were set. This means multiple float return values get packed in %f0,
%f1, %f2, ...
Note that when returning a struct in registers, clang will set the
'inreg' flag on the return value, so that behavior is unchanged. This
also happens when returning a float _Complex.
llvm-svn: 199028
2014-01-12 04:13:17 +00:00
a66b314c34
[Sparc] Add missing processor types: v7 and niagara
...
llvm-svn: 199024
2014-01-11 23:56:13 +00:00
0653218b2b
[Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify-machineinstrs with SPARC backend.
...
llvm-svn: 199014
2014-01-11 19:38:03 +00:00
ad40dfcb4b
[Sparc] Emit retl/ret instead of jmp instruction. It improves the readability of the assembly generated.
...
llvm-svn: 198910
2014-01-10 02:55:27 +00:00
0d288d3105
[Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl.
...
llvm-svn: 198909
2014-01-10 01:48:17 +00:00
6ff62cc539
[Sparc] Multiclass for loads/stores. No functionality change intended.
...
llvm-svn: 198893
2014-01-09 21:49:18 +00:00
b7c6965b19
[SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly.
...
llvm-svn: 198740
2014-01-08 07:47:57 +00:00
f691e2c230
[Sparc] Correct the mask for fixup_sparc_br19.
...
llvm-svn: 198739
2014-01-08 06:46:51 +00:00
b3b7c38983
[Sparc] Add support for parsing branch instructions and conditional moves.
...
llvm-svn: 198738
2014-01-08 06:14:52 +00:00
894843cb4e
Move the llvm mangler to lib/IR.
...
This makes it available to tools that don't link with target (like llvm-ar).
llvm-svn: 198708
2014-01-07 21:19:40 +00:00
8a8cd2bab9
Re-sort all of the includes with ./utils/sort_includes.py so that
...
subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.
Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.
llvm-svn: 198685
2014-01-07 11:48:04 +00:00
559c4ac377
[Sparc] Add support for parsing sparc asm modifiers such as %hi, %lo etc.,
...
Also, correct the offsets for FixupsKindInfo.
llvm-svn: 198681
2014-01-07 08:00:49 +00:00
0458b599f8
[Sparc] Add support for parsing memory operands in sparc AsmParser.
...
llvm-svn: 198658
2014-01-07 01:49:11 +00:00
2bab98bbae
[Sparc] Explicitly cast -1 to unsigned to fix buildbot errors.
...
llvm-svn: 198592
2014-01-06 08:24:44 +00:00
dfcccc7db0
[Sparc] Add initial implementation of disassembler for sparc
...
llvm-svn: 198591
2014-01-06 08:08:58 +00:00
13199b17f8
Remove unnecessary #includes.
...
llvm-svn: 198585
2014-01-06 06:00:00 +00:00
b73aeca888
[Sparc] Add ELF Object Writer for Sparc.
...
llvm-svn: 198580
2014-01-06 01:22:54 +00:00
908bf814e7
Refactor function that checks that __builtin_returnaddress's argument is constant.
...
This moves the check up into the parent class so that all targets can use it
without having to copy (and keep in sync) the same error message.
llvm-svn: 198579
2014-01-06 00:43:20 +00:00
db5122f6da
SPARC: Make helper function static.
...
llvm-svn: 198567
2014-01-05 20:26:05 +00:00
5f1cce50e6
[Sparc] Add initial implementation of MC Code emitter for sparc.
...
llvm-svn: 198533
2014-01-05 02:13:48 +00:00
df7dd28dc8
Emit an error message if the value passed to __builtin_returnaddress isn't a constant
...
__builtin_returnaddress requires that the value passed into is be a constant.
However, at -O0 even a constant expression may not be converted to a constant.
Emit an error message intead of crashing.
llvm-svn: 198531
2014-01-05 01:47:20 +00:00
c2dee7dc74
[Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.
...
llvm-svn: 198484
2014-01-04 11:30:13 +00:00
96ab3bc5bd
[SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64.
...
Fixes PR18356.
llvm-svn: 198480
2014-01-04 07:17:21 +00:00
58873566b3
Make the llvm mangler depend only on DataLayout.
...
Before this patch any program that wanted to know the final symbol name of a
GlobalValue had to link with Target.
This patch implements a compromise solution where the mangler uses DataLayout.
This way, any tool that already links with Target (llc, clang) gets the exact
behavior as before and new IR files can be mangled without linking with Target.
With this patch the mangler is constructed with just a DataLayout and DataLayout
is extended to include the information the Mangler needs.
llvm-svn: 198438
2014-01-03 19:21:54 +00:00
9a3da52ea2
[Sparc] Handle atomic loads/stores in sparc backend.
...
llvm-svn: 198286
2014-01-01 22:11:54 +00:00
77011e861b
[SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order.
...
llvm-svn: 198281
2014-01-01 20:22:45 +00:00
acf0233a46
[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.
...
llvm-svn: 198280
2014-01-01 19:00:10 +00:00
3e3a29a2e9
[SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
...
This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.
llvm-svn: 198157
2013-12-29 07:15:09 +00:00
5ac9c8faec
[SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall().
...
This makes the sparc backend to generate Sparc64 ABI compliant code.
llvm-svn: 198149
2013-12-29 04:27:21 +00:00
0776cc0acd
[SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.
...
Also, pass fp128 arguments to varargs through integer registers if necessary.
llvm-svn: 198145
2013-12-29 01:20:36 +00:00
bf683fd15c
[Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.
...
llvm-svn: 198030
2013-12-26 01:49:59 +00:00
08bcf29068
[Sparc] Add target specific MCExpr class to handle sparc specific modifiers like %hi, %lo, etc.,
...
llvm-svn: 198029
2013-12-26 00:01:52 +00:00
0b938652d3
[Sparc] Add MCInstPrinter implementation for SPARC.
...
llvm-svn: 198028
2013-12-25 23:43:39 +00:00
2fc7101e3c
Add stack alignment information for Sparc.
...
This matches the data in clang which was added by Jakob Stoklund Olesen in
r179596.
Thanks for erikjv on irc for pointing me to the relevant documents:
http://sparc.com/standards/64.psabi.1.35.ps.Z
page 25: Every stack frame must be 16-byte aligned.
http://sparc.com/standards/psABI3rd.pdf
page 3-10: Although the architecture requires only word alignment, software convention and the operating system require every stack frame to be doubleword aligned.
I tried to add a test, but it looks like sparc doesn't implement dynamic stack
realignment. This will be tested in clang shortly.
llvm-svn: 197646
2013-12-19 02:21:16 +00:00
bccb9d45ad
The preferred alignment defaults to the abi alignment. Omit if it is the same.
...
llvm-svn: 197400
2013-12-16 18:01:51 +00:00
8afbb28cea
On DataLayout, omit the default of p:64:64:64.
...
llvm-svn: 197397
2013-12-16 17:15:29 +00:00
1caa693a7b
Assume defaults to produce smaller datalayout strings.
...
llvm-svn: 197249
2013-12-13 17:56:11 +00:00
60f48e5a67
Move Sparc's getDataLayout out of line and add comments.
...
llvm-svn: 196990
2013-12-11 01:07:43 +00:00
8bc9bfaa5a
Prune redundant dependencies in LLVMBuild.txt.
...
llvm-svn: 196988
2013-12-11 00:30:57 +00:00
61116e7084
[SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9.
...
llvm-svn: 196755
2013-12-09 05:13:25 +00:00
f6c8fe983b
[Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error.
...
llvm-svn: 196751
2013-12-09 04:02:15 +00:00
72cc248524
[SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9.
...
This fixes PR18150.
llvm-svn: 196735
2013-12-08 22:06:07 +00:00
5113d166f5
Refactor the setting of PrivateGlobalPrefix.
...
No functionality change.
llvm-svn: 196170
2013-12-02 23:39:26 +00:00
50712a456d
Change the default of AsmWriterClassName and isMCAsmWriter.
...
llvm-svn: 196065
2013-12-02 04:55:42 +00:00
226e10edff
[CMake] Let add_public_tablegen_target() provide intrinsics_gen, too.
...
I think, in principle, intrinsics_gen may be added explicitly.
That said, it can be added incidentally, since each target already has dependencies to llvm-tblgen.
Almost all source files depend on both CommonTaleGen and intrinsics_gen.
Explicit add_dependencies() have been pruned under lib/Target.
llvm-svn: 195929
2013-11-28 17:04:31 +00:00
ce746c6c49
[CMake] Let add_public_tablegen_target responsible to provide dependency to CommonTableGen.
...
add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS.
LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope.
llvm-svn: 195927
2013-11-28 17:04:04 +00:00
413518f1f8
[CMake] Prune include_directories() in llvm/lib/Target. add_llvm_target() sets them.
...
llvm-svn: 195921
2013-11-28 14:53:30 +00:00
edbeaee857
SparcFrameLowering.cpp: Prune 'DL' [-Wunused-variable]
...
llvm-svn: 195590
2013-11-25 00:52:46 +00:00
1116868a0d
[Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64.
...
llvm-svn: 195576
2013-11-24 20:23:25 +00:00
9c338504e5
[Sparc]: Implement LEA pattern for sparcv9.
...
llvm-svn: 195575
2013-11-24 20:07:35 +00:00
f79528c132
[SparcV9]: Do not emit .register directives for global registers that are clobbered by calls but not used in the function itself.
...
llvm-svn: 195574
2013-11-24 18:41:49 +00:00
0510db0597
[SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64.
...
llvm-svn: 195573
2013-11-24 17:41:41 +00:00
d12ccbd343
[weak vtables] Remove a bunch of weak vtables
...
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
llvm-svn: 195064
2013-11-19 00:57:56 +00:00
49109a279c
Revert r194865 and r194874.
...
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.
llvm-svn: 194997
2013-11-18 09:31:53 +00:00
dbedae89b9
[weak vtables] Remove a bunch of weak vtables
...
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
llvm-svn: 194865
2013-11-15 22:34:48 +00:00
b6517850fb
Expand rotate instructions on sparcv9 as well.
...
llvm-svn: 194500
2013-11-12 19:04:45 +00:00
5ae77f7564
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode.
...
llvm-svn: 193957
2013-11-03 12:28:40 +00:00
f1d807ee13
[Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128.
...
llvm-svn: 193947
2013-11-03 08:00:19 +00:00
5615aca219
[SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap.
...
llvm-svn: 193941
2013-11-03 05:59:07 +00:00
2262cfaf19
SparcV9 doesnt have rem instruction either.
...
llvm-svn: 193789
2013-10-31 19:22:33 +00:00
79858aa3df
Add a helper getSymbol to AsmPrinter.
...
llvm-svn: 193627
2013-10-29 17:07:16 +00:00
43c4e24fad
Add a MCAsmInfoELF class and factor some code into it.
...
We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before.
llvm-svn: 192760
2013-10-16 01:34:32 +00:00
8812485d41
[Sparc] Disable tail call optimization for sparc64.
...
This patch fixes PR17506.
llvm-svn: 192294
2013-10-09 12:50:39 +00:00
c22f85331c
SparcJITInfo.cpp: Prune "default:" label to fix a warning. [-Wcovered-switch-default]
...
llvm-svn: 192179
2013-10-08 10:29:09 +00:00
2949f670d5
Prune trailing linefeeds.
...
llvm-svn: 192178
2013-10-08 10:29:03 +00:00
2ea4c2880c
[Sparc] Implement JIT for SPARC.
...
No new testcases. However, this patch makes all supported JIT testcases in
test/ExecutionEngine pass on Sparc.
llvm-svn: 192176
2013-10-08 07:15:22 +00:00
8223c553cf
[Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead.
...
llvm-svn: 192160
2013-10-08 02:50:29 +00:00
e90fd9c5e0
Remove getEHExceptionRegister and getEHHandlerRegister.
...
They haven't been used for a long time. Patch by MathOnNapkins.
llvm-svn: 192099
2013-10-07 13:39:22 +00:00
f482d3d338
[Sparc] Do not emit nop after fcmp* instruction with V9.
...
llvm-svn: 192056
2013-10-06 07:06:44 +00:00
572d5057e3
[Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.
...
This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.
llvm-svn: 192054
2013-10-06 03:36:18 +00:00
1230342fd2
[Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.
...
addx/subx does not modify conditional codes whereas addxcc/subxx does.
llvm-svn: 192053
2013-10-06 02:11:10 +00:00
ece63dbd0d
[Sparc] Use correct alignment while loading/storing fp128 values.
...
llvm-svn: 192023
2013-10-05 02:29:47 +00:00
30781deb1c
[Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand.
...
llvm-svn: 192015
2013-10-05 00:31:41 +00:00
84f1523cac
[Sparc] Correct the floating point conditional code mapping in GetOppositeBranchCondition().
...
llvm-svn: 192006
2013-10-04 23:54:30 +00:00
4c0cdd734c
[Sparc] Implements exception handling in SPARC with DwarfCFI.
...
llvm-svn: 191432
2013-09-26 15:11:00 +00:00
94629eb861
[Sparc] Use correct instruction pattern for CMPri.
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llvm-svn: 191180
2013-09-22 18:54:54 +00:00
51270837aa
[Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter.
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llvm-svn: 191168
2013-09-22 09:54:42 +00:00
709d154d69
[Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended.
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llvm-svn: 191167
2013-09-22 09:18:26 +00:00
2fb440fbad
[Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.
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llvm-svn: 191166
2013-09-22 08:51:55 +00:00
31d093c705
ISelDAG: spot chain cycles involving MachineNodes
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Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
llvm-svn: 191165
2013-09-22 08:21:56 +00:00
cb1dca602c
[Sparc] Add support for TLS in sparc.
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llvm-svn: 191164
2013-09-22 06:48:52 +00:00
7e7eb8ce69
[SPARC] Make functions with GLOBAL_OFFSET_TABLE access as non-leaf functions.
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llvm-svn: 191160
2013-09-22 01:40:24 +00:00
e9ef51222b
[Sparc] Emit .register directive to declare the use of global registers %g2, %g4, %g6 and %g7.
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llvm-svn: 191158
2013-09-22 00:42:30 +00:00
829aec5900
[Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets.
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llvm-svn: 191154
2013-09-21 23:51:08 +00:00
55ecb10e99
[Sparc] Correctly handle call to functions with ReturnsTwice attribute.
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In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.
This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.
llvm-svn: 190033
2013-09-05 05:32:16 +00:00
b803cec00e
[Sparc] Fix an assertion failure while lowering fcmp on long double.
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This assertion is triggered because an integer constant is created with wrong
type.
llvm-svn: 189948
2013-09-04 15:15:20 +00:00
59039dc1bf
[Sparc] Add support for soft long double (fp128).
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llvm-svn: 189780
2013-09-03 04:11:59 +00:00
01cb19f93c
[Sparc] Implement spill and load for long double(f128) registers.
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llvm-svn: 189768
2013-09-02 18:32:45 +00:00
35e0c382d5
[Sparc] Add long double (f128) instructions to sparc backend.
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llvm-svn: 189198
2013-08-25 18:30:06 +00:00
12d8089b8e
[Sparc] Added V9's extra floating point registers and their aliases.
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llvm-svn: 189195
2013-08-25 17:03:02 +00:00
0c00704f27
Use register masks on SPARC call instructions.
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llvm-svn: 189085
2013-08-23 02:33:47 +00:00
a8960a1f7c
Add an OtherPreserved field to the CalleeSaved TableGen class.
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This field specifies registers that are preserved across function calls,
but that should not be included in the generates SaveList array.
This can be used ot generate regmasks for architectures that save
registers through other means, like SPARC's register windows.
llvm-svn: 189084
2013-08-23 02:25:47 +00:00
f625773bca
[Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.
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llvm-svn: 188738
2013-08-20 01:26:14 +00:00
b50bf5a0e3
[Sparc] Enable xword directive in sparcv9.
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llvm-svn: 188141
2013-08-10 20:13:20 +00:00
aaf66c7357
Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.
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Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.
llvm-svn: 187780
2013-08-06 06:38:37 +00:00
fee76fac2f
[Sparc] Rewrite MBB's live-in registers for leaf functions. Also, add
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register i7 as a live-in if current function's return address is taken.
This revision fixes PR16269.
llvm-svn: 187433
2013-07-30 19:53:10 +00:00
fdcc498a25
[Sparc] Use call's debugloc for the unimp instruction.
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llvm-svn: 187402
2013-07-30 02:26:29 +00:00
b94011fd28
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
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llvm-svn: 186274
2013-07-14 04:42:23 +00:00
6f0b450530
[Sparc]: Add memory operands for the frame references in the storeRegToStackSlot
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and loadRegFromStackSlot.
llvm-svn: 184935
2013-06-26 12:40:16 +00:00
295bd43adb
The getRegForInlineAsmConstraint function should only accept MVT value types.
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llvm-svn: 184642
2013-06-22 18:37:38 +00:00
a3cd350249
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
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llvm-svn: 184360
2013-06-19 21:36:55 +00:00
b735b4d6db
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
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Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
llvm-svn: 184067
2013-06-16 20:34:27 +00:00
7dae9ce021
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.
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llvm-svn: 183613
2013-06-08 15:32:59 +00:00
fdc9d0a991
Remember the anyext patterns.
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llvm-svn: 183589
2013-06-07 22:59:29 +00:00
9f812b97ba
Add missing zextloadi1 to i64 patterns. PR16721.
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llvm-svn: 183587
2013-06-07 22:55:05 +00:00
6235c06ff8
Don't cache the instruction and register info from the TargetMachine, because
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the internals of TargetMachine could change.
No functionality change intended.
llvm-svn: 183565
2013-06-07 20:35:25 +00:00
158d8069ad
Fix a typo in asm string of BP* family of instructions. With this fix
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I am able to compile/assemble/link/run /bin/echo from FreeBSD.
llvm-svn: 183537
2013-06-07 17:46:57 +00:00
dc82ac0dcc
[Sparc]: Use cmp instruction instead of subcc to compare integers.
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llvm-svn: 183463
2013-06-07 00:03:36 +00:00
f77190855d
Cache the TargetLowering info object as a pointer.
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Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
llvm-svn: 183361
2013-06-06 00:43:09 +00:00
a54533ed78
Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,
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llvm-svn: 183243
2013-06-04 18:33:25 +00:00
f80d72f149
Sparc: Add support for indirect branch and blockaddress in Sparc backend.
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llvm-svn: 183094
2013-06-03 05:58:33 +00:00
774fe2e29a
Sparc: When storing 0, use %g0 directly in the store instruction instead of
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using two instructions (sethi and store).
llvm-svn: 183090
2013-06-03 00:21:54 +00:00
0bbe1b210e
Sparc: Combine add/or/sethi instruction with restore if possible.
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llvm-svn: 183088
2013-06-02 21:48:17 +00:00
3e8c7d98be
Sparc: Perform leaf procedure optimization by default
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llvm-svn: 183083
2013-06-02 02:24:27 +00:00
Venkatraman Govindaraju