d9d18aff6a
Define BR in the .td file now that Evan made tblgen smarter.
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llvm-svn: 24589
2005-12-04 18:42:54 +00:00
048b26387b
Represent the encoding of the SPR instructions as they actually are, so
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that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
llvm-svn: 24521
2005-11-29 22:42:50 +00:00
c138118cdb
Add the remainder of the AltiVec 4 x float instructions. Further
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enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
llvm-svn: 24516
2005-11-29 08:04:45 +00:00
11fd6b22b1
Small tweaks noticed while on the plane.
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llvm-svn: 24492
2005-11-26 22:39:34 +00:00
8492fd30ab
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
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Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
llvm-svn: 24489
2005-11-23 05:29:52 +00:00
b439dad538
Allow pseudos to have patterns, no functionality change
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llvm-svn: 23988
2005-10-25 20:58:43 +00:00
74ab9960f2
Added InstrSchedClass to each of the PowerPC Instructions.
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Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
llvm-svn: 23830
2005-10-19 19:51:16 +00:00
9f3c26c4ea
Write patterns for the various shl and srl patterns that don't involve
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doing something clever.
llvm-svn: 23824
2005-10-19 18:42:01 +00:00
7503d46feb
Rename PowerPC*.td -> PPC*.td
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llvm-svn: 23740
2005-10-14 23:40:39 +00:00
Chris Lattner