Commit Graph

2242 Commits

Author SHA1 Message Date
Andrea Di Biagio 4729d1ff27 [llvm-mca] Add another test for partial register stalls.
This test checks that a physical register is correctly allocated for the partial
write to register BX.
The ADD instruction has to wait for the write to RBX (and BX) before being
executed.

llvm-svn: 334730
2018-06-14 15:54:34 +00:00
Andrea Di Biagio 0ffb2271a1 [llvm-mca] Fixed a bug in the logic that checks if a memory operation is ready to execute.
Fixes PR37790.

In some (very rare) cases, the LSUnit (Load/Store unit) was wrongly marking a
load (or store) as "ready to execute" effectively bypassing older memory barrier
instructions.

To reproduce this bug, the memory barrier must be the first instruction in the
input assembly sequence, and it doesn't have to perform any register writes.

llvm-svn: 334633
2018-06-13 18:30:14 +00:00
Pavel Labath 4adc88ed25 [DWARF/AccelTable] Remove getDIESectionOffset for DWARF v5 entries
Summary:
This method was not correct for entries in DWO files as it assumed it
could just add up the CU and DIE offsets to get the absolute DIE offset.
This is not correct for the DWO files, as here the CU offset will
reference the skeleton unit, whereas the DIE offset will be the offset
in the full unit in the DWO file.

Unfortunately, this means that we are not able to determine the absolute
DIE offset using the information in the .debug_names section alone,
which means we have to offload some of this work to the users of this
class.

To demonstrate how this can be done, I've added/fixed the ability to
lookup entries using accelerator tables in DWO files in llvm-dwarfdump.
To make this happen, I've needed to make two extra changes in other
classes:
- made the DWARFContext method to lookup a CU based on the section
  offset public. I've needed this functionality to lookup a CU, and this
  seems like a useful thing in general.
- made DWARFUnit::getDWOId call extractDIEsIfNeeded. Before this, the
  DWOId was filled in only if the root DIE happened to be parsed
  before we called the accessor. Since the lazy parsing is supposed to
  happen under the hood, calling extractDIEsIfNeeded seems appropriate.

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D48009

llvm-svn: 334578
2018-06-13 08:14:27 +00:00
Clement Courbet 7db69cc08a [X86] Fix skylake server scheduling info.
Summary:
This fixes most of the scheduling info for SKX vector operations.
I had to split a lot of the YMM/ZMM classes into separate classes for YMM and ZMM.

The before/after llvm-exegesis analysis are in the phabricator diff.

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47721

llvm-svn: 334407
2018-06-11 14:37:53 +00:00
Simon Pilgrim 89deac6694 [X86][BtVer2] Add support for all SUB/XOR 32/64 scalar instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), these instructions are dependency breaking and fast-path zero the destination register (and appropriate EFLAGS bits).

llvm-svn: 334303
2018-06-08 17:00:45 +00:00
Simon Pilgrim efb4806bb9 [X86][BtVer2] Remove SBB tests that were accidentally added in rL334296
These aren't true zero-idiom instructions (just dependency breaking).

llvm-svn: 334297
2018-06-08 15:43:00 +00:00
Simon Pilgrim 53766a986d [X86][BtVer2] Add tests for scalar SUB/XOR instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions).

llvm-svn: 334296
2018-06-08 15:28:43 +00:00
Simon Pilgrim aafcf9e4a1 [X86][BtVer2] Limit zero idiom tests to a single iteration.
Reduces output size and we're only wanting to check that the instructions are fast-path'd (just Dispatch+Retire) anyhow

llvm-svn: 334292
2018-06-08 15:01:40 +00:00
Paul Semel e57bc78324 [llvm-strip] Expose --strip-unneeded option
Differential Revision: https://reviews.llvm.org/D47818

llvm-svn: 334182
2018-06-07 10:05:25 +00:00
Peter Collingbourne cf017ada68 llvm-readobj: fix printing number of relocations in Android packed format.
With '-elf-output-style=GNU -relocations', a header containing the number
of entries is printed before all the relocation entries in the section.
For Android packed format, we need to perform the unpacking first before
we can get the actual number of relocations in the section.

Patch by Rahul Chaudhry!

Differential Revision: https://reviews.llvm.org/D47800

llvm-svn: 334147
2018-06-07 00:02:07 +00:00
Alexander Shaposhnikov 29407f3abe [llvm-strip] Expose --discard-all option
Expose objcopy's --discard-all option in llvm-strip.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D47750

llvm-svn: 334131
2018-06-06 21:23:19 +00:00
Simon Pilgrim aef5bdbea1 [X86][BtVer2] Add support for all vector instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), all these instructions are dependency breaking and zero the destination register.

llvm-svn: 334119
2018-06-06 19:06:09 +00:00
Simon Pilgrim 7a48bb6e44 [llvm-mca][x86] Fix all resources-x86_64.s tests to use different registers in reg-reg cases
I noticed while working on zero-idiom + dependency-breaking support (PR36671) that most of our binary instruction tests were reusing the same src registers, which would cause the tests to fail once we enable scalar zero-idiom support on btver2. Fixed in all targets to keep them in sync.

llvm-svn: 334110
2018-06-06 18:20:25 +00:00
Simon Pilgrim 64541ff297 [X86][BtVer2] Add tests for all vector instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), all these instructions are dependency breaking and zero the destination register.

TODO: Scalar instructions still need to be tested (need to check EFLAGS handling).
llvm-svn: 334104
2018-06-06 16:14:37 +00:00
Sanjay Patel 59313be8d3 [CodeGen] assume max/default throughput for unspecified instructions
This is a fix for the problem arising in D47374 (PR37678):
https://bugs.llvm.org/show_bug.cgi?id=37678

We may not have throughput info because it's not specified in the model 
or it's not available with variant scheduling, so assume that those
instructions can execute/complete at max-issue-width.

Differential Revision: https://reviews.llvm.org/D47723

llvm-svn: 334055
2018-06-05 23:34:45 +00:00
Andrea Di Biagio 757600bccb [llvm-mca] Correctly update the CyclesLeft of a register read in the presence of partial register updates.
This patch fixe the logic in ReadState::cycleEvent(). That method was not
correctly updating field `TotalCycles`.

Added extra code comments in class ReadState to better describe each field.

llvm-svn: 334028
2018-06-05 17:12:02 +00:00
Alexander Shaposhnikov d7eaf27654 [llvm-strip] Add missing aliases for --strip-debug
Add missing aliases for --strip-debug: -g, -S, -d.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D47674

llvm-svn: 333940
2018-06-04 18:55:41 +00:00
Andrea Di Biagio 39e5a5695f [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca.
This patch is the last of a sequence of three patches related to LLVM-dev RFC
"MC support for variant scheduling classes".
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html

This fixes PR36672.

The main goal of this patch is to teach llvm-mca how to solve variant scheduling
classes.  This patch does that, plus it adds new variant scheduling classes to
the BtVer2 scheduling model to identify so-called zero-idioms (i.e. so-called
dependency breaking instructions that are known to generate zero, and that are
optimized out in hardware at register renaming stage).

Without the BtVer2 change, this patch would not have had any meaningful tests.
This patch is effectively the union of two changes:
 1) a change that teaches llvm-mca how to resolve variant scheduling classes.
 2) a change to the BtVer2 scheduling model that allows us to special-case
    packed XOR zero-idioms (this partially fixes PR36671).

Differential Revision: https://reviews.llvm.org/D47374 

llvm-svn: 333909
2018-06-04 15:43:09 +00:00
Alexander Ivchenko ab60a2823f [llvm-readobj] Support GNU_PROPERTY_X86_FEATURE_1_AND notes in .note.gnu.property
Resubmit of r333424. This version contains the fix for fails found by buildbots
on some targets.

This patch allows parsing GNU_PROPERTY_X86_FEATURE_1_AND
notes in .note.gnu.property sections. These notes
indicate that the object file is built to support Intel CET.

patch by mike.dvoretsky

Differential Revision: https://reviews.llvm.org/D47473

llvm-svn: 333908
2018-06-04 15:14:18 +00:00
Greg Bedwell bbe64af0a0 [llvm-mca] Regenerate a test to remove a double newline
Command used: py update_mca_test_checks.py ..\test\tools\llvm-mca\*\*.s ..\test\tools\llvm-mca\*\*\*.s

llvm-svn: 333893
2018-06-04 12:30:03 +00:00
Roman Lebedev 7b53d1454f [llvm-mca] Make sure not to end the test files with an empty line.
Summary:
It's super irritating.

[properly configured] git client then complains about that double-newline,
and you have to use `--force` to ignore the warning, since even if you
fix it manually, it will be reintroduced the very next runtime :/

Reviewers: RKSimon, andreadb, courbet, craig.topper, javed.absar, gbedwell

Reviewed By: gbedwell

Subscribers: javed.absar, tschuett, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D47697

llvm-svn: 333887
2018-06-04 11:48:46 +00:00
Paul Semel 46201fb7bc [llvm-objcopy] Fix null symbol handling
This fixes the bug where strip-all option was
leading to a malformed outputted ELF file.

Differential Revision: https://reviews.llvm.org/D47414

llvm-svn: 333772
2018-06-01 16:19:46 +00:00
Alexander Shaposhnikov ecc84834b7 [llvm-strip] Add -o option to llvm-strip
This diff implements the option -o 
for specifying a file to write the output to.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D47505

llvm-svn: 333693
2018-05-31 20:42:13 +00:00
Clement Courbet 2e41c5a79c [X86] Introduce WriteFLDC for x87 constant loads.
Summary:
{FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI} were using WriteMicrocoded.

 - I've measured the values for Broadwell, Haswell, SandyBridge, Skylake.
 - For ZnVer1 and Atom, values were transferred form InstRWs.
 - For SLM and BtVer2, I've guessed some values :(

Reviewers: RKSimon, craig.topper, andreadb

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D47585

llvm-svn: 333656
2018-05-31 14:22:01 +00:00
Clement Courbet b78ab5097d [X86] Extract latency of fldz/fld1 in separate classes.
Summary:
 - I've measured the values for Broadwell, Haswell, SandyBridge, Skylake.
 - For ZnVer1 and Atom, values were transferred form `InstRW`s.
 - For SLM and BtVer2, values are from Agner.

This is split off from https://reviews.llvm.org/D47377

Reviewers: RKSimon, andreadb

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D47523

llvm-svn: 333642
2018-05-31 11:41:27 +00:00
Pavel Labath 59870af66f DWARFAcceleratorTable: fix equal_range iterators
Summary:
Both (Apple and DWARF5) implementations of the iterators had bugs which
resulted in crashes if one attempted to iterate through the accelerator
tables all the way.

For the Apple tables, the issue was that we did not clear the DataOffset
field when we reached the end, which made our iterator compare unequal
to the "end" iterator. For the Dwarf5 tables, the problem was that we
incremented the CurrentIndex pointer and then used the incremented
(possibly invalid) pointer to check whether we have reached the end of
the index list.

The reason these bugs went undetected is because their only user
(dwarfdump) only ever searched for the first match. Besides allowing us
to test this fix, changing llvm-dwarfdump --find to display all matches
seems like a good improvement (it makes the behavior consistent with the
--name option), so I change llvm-dwarfdump to do that.

The existing tests would be sufficient to test this fix with the new
llvm-dwarfdump behavior, but I add a special test that demonstrates that
the tool indeed displays multiple results. The find.test test needed to
be tweaked a bit as the tool now does not print the ".debug_info
contents" header (also consistent with how --name works).

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D47543

llvm-svn: 333635
2018-05-31 08:47:00 +00:00
Vedant Kumar e3c1fb8b12 [llvm-cov] Use the new PrintHTMLEscaped utility
This removes some duplicate logic to escape characters in HTML output.

llvm-svn: 333608
2018-05-30 23:35:14 +00:00
Peter Collingbourne 1651ac13be llvm-objcopy: Set sh_link to 0 on unrecognized symtab-linked sections.
Per discussion on the generic-abi mailing list:
https://groups.google.com/forum/#!topic/generic-abi/MPr8TVtnVn4

An object file manipulation tool must either write out a symbol
table with the same number of entries as the original symbol table
and in the same order, or if this is impossible, refuse to operate
on the object file if it has unrecognized sections that are linked
to the symtab section. However, existing tools (namely GNU strip,
GNU objcopy and ld.{bfd,gold,lld} -r) do not comply with this at
present: they change symbol table indexes and set sh_link to 0 on
the unrecognized symtab-linked sections.

We intend to use the latter as a (temporary) signal that a tool has
operated on a proposed new symtab-linked section and invalidated the
symbol table indexes. However, llvm-objcopy currently keeps sh_link
pointing to the new symtab section. This patch changes llvm-objcopy
to set sh_link to 0 to match the behaviour of the other tools.

Differential Revision: https://reviews.llvm.org/D47404

llvm-svn: 333581
2018-05-30 19:30:39 +00:00
Galina Kistanova df917811ca Reverted r333424 as it broke multiple build bots and left unfixed for a long time
llvm-svn: 333578
2018-05-30 18:51:08 +00:00
Jonas Devlieghere f4ce54a123 [dsymutil] Escape HTML special characters in plist.
When printing string in the Plist, we weren't escaping the characters
which lead to invalid XML. This patch adds the escape logic to
StringExtras.

rdar://39785334

llvm-svn: 333565
2018-05-30 17:47:11 +00:00
Alexander Ivchenko 6572425462 [llvm-readobj] Support GNU_PROPERTY_X86_FEATURE_1_AND notes in .note.gnu.property
This patch allows parsing GNU_PROPERTY_X86_FEATURE_1_AND
notes in .note.gnu.property sections. These notes
indicate that the object file is built to support Intel CET.

patch by mike.dvoretsky

Differential Revision: https://reviews.llvm.org/D47473

llvm-svn: 333424
2018-05-29 14:49:51 +00:00
Clement Courbet 07c9ec6f2e [X86][Sched] Add InstRW for CLC on Intel after SNB.
Summary:
After SNB, Intel CPUs can rename CF independently of other EFLAGS,
so the renamer can zero it for free. Note that STC still consumes resources.

To reproduce: `$ llvm-exegesis -mode=uops -opcode-name=CLC`

On SNB:
```
---
key:
  opcode_name:     CLC
  mode:            uops
  config:          ''
cpu_name:        sandybridge
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: '3', value: 0.0014, debug_string: SBPort0 }
  - { key: '4', value: 0.0013, debug_string: SBPort1 }
  - { key: '5', value: 0.0003, debug_string: SBPort4 }
  - { key: '6', value: 0.0029, debug_string: SBPort5 }
  - { key: '10', value: 0.0003, debug_string: SBPort23 }
error:           ''
info:            'instruction is serial, repeating a random one.
Snippet:
CLC
'
...
```

On HSW:
```
---
key:
  opcode_name:     CLC
  mode:            uops
  config:          ''
cpu_name:        haswell
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: '3', value: 0.001, debug_string: HWPort0 }
  - { key: '4', value: 0.0009, debug_string: HWPort1 }
  - { key: '5', value: 0.0004, debug_string: HWPort2 }
  - { key: '6', value: 0.0006, debug_string: HWPort3 }
  - { key: '7', value: 0.0002, debug_string: HWPort4 }
  - { key: '8', value: 0.0012, debug_string: HWPort5 }
  - { key: '9', value: 0.0022, debug_string: HWPort6 }
  - { key: '10', value: 0.0001, debug_string: HWPort7 }
error:           ''
info:            'instruction is serial, repeating a random one.
Snippet:
CLC
'
...

```

Reviewers: craig.topper, RKSimon

Subscribers: gchatelet, llvm-commits

Differential Revision: https://reviews.llvm.org/D47362

llvm-svn: 333392
2018-05-29 06:19:39 +00:00
Jonas Devlieghere cb547cbb5c [dwarfdump] Make -c and -p work together
When requesting to dump both the parent chain and children, we used to
print the DIE more than once because we propagated the dump options to
the parent without clearing the respective flags. This commit fixes this
oversight and adds a test.

rdar://39415292

Differential revision: https://reviews.llvm.org/D47263

llvm-svn: 333350
2018-05-26 19:39:56 +00:00
Paul Semel cf51c80bf1 [llvm-objcopy] Add --keep-file-symbols option
This option prevent from removing file symbols while removing symbols.

Differential Revision: https://reviews.llvm.org/D46830

llvm-svn: 333339
2018-05-26 08:10:37 +00:00
Simon Pilgrim 0155bf0da9 [X86][SNB] Fix differences between vex/non-vex XMM vector moves (PR37286)
As confirmed by llvm-exegesis, there is no scheduler difference between MOVDQA/MOVDQU and VMOVDQA/VMOVDQU xmm reg-reg moves

Another chapter in the never ending crusade to remove useless InstRW overrides from the x86 scheduler models......

llvm-svn: 333271
2018-05-25 12:18:11 +00:00
Paul Semel 99dda0bab8 [llvm-objcopy] Add --strip-unneeded option
Differential Revision: https://reviews.llvm.org/D46896

llvm-svn: 333267
2018-05-25 11:01:25 +00:00
Greg Bedwell e790f6fb06 [UpdateTestChecks] Improved update_mca_test_checks block analysis
Previously update_mca_test_checks worked entirely at "block" level where
a block is some sequence of lines delimited by at least one empty line.
This generally worked well, but could sometimes lead to excessive
repetition of check lines for various prefixes if some block was almost
identical between prefixes, but not quite (for example, due to a
different dispatch width in the otherwise identical summary views).

This new analyis attempts to split blocks further in the case where the
following conditions are met:
  a) There is some prefix common to every RUN line (typically 'ALL').
  b) The first line of the block is common to the output with every prefix.
  c) The block has the same number of lines for the output with every prefix.

Also, regenerated all llvm-mca test files with the following command:
update_mca_test_checks.py "../test/tools/llvm-mca/*/*.s" "../test/tools/llvm-mca/*/*/*.s"

The new analysis showed a "multiple lines not disambiguated by prefixes" warning
for test "AArch64/Exynos/scheduler-queue-usage.s" so I've also added some
explicit prefixes to each of the RUN lines in that test.

Differential Revision: https://reviews.llvm.org/D47321

llvm-svn: 333204
2018-05-24 16:36:44 +00:00
Jonas Devlieghere 27126f5260 [Support] Add color cl category.
This commit adds a color category so tools can document this option and
enables it for dwarfdump and dsymuttil.

rdar://problem/40498996

llvm-svn: 333176
2018-05-24 11:36:57 +00:00
Alexander Shaposhnikov c7277e6e2b [llvm-strip] Minor fix of the usage of TableGen
This is a small follow-up to the revisions r333117 and r331663.

1. Avoid the name conflicts of the generated variables for prefixes.
2. Apply clang-format -i -style=llvm to llvm-objcopy.cpp once again.
3. Add a test for the flag with double dash.

Test plan: make check-all

llvm-svn: 333120
2018-05-23 20:39:52 +00:00
Alexander Shaposhnikov 35bee3e06b [llvm-strip] Expose --keep-symbol option
Expose --keep-symbol option in llvm-strip.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D47222

llvm-svn: 333117
2018-05-23 19:44:19 +00:00
Andrea Di Biagio 3fc20c9c7f [llvm-mca] Print the "Block RThroughput" in the SummaryView.
This patch implements the "block reciprocal throughput" computation in the
SummaryView.

The block reciprocal throughput is computed as the MAX of:
  - NumMicroOps / DispatchWidth
  - Resource Cycles / #Units   (for every resource consumed).

The block throughput is bounded from above by the hardware dispatch throughput.
That is because the DispatchWidth is an upper bound on how many opcodes can be part
of a single dispatch group.

The block throughput is also limited by the amount of hardware parallelism. The
number of available resource units affects how the resource pressure is
distributed, and also how many blocks can be delivered every cycle.

llvm-svn: 333095
2018-05-23 15:59:27 +00:00
Alexander Shaposhnikov 6e7814c484 [llvm-objcopy] Fix the behavior of --strip-* and --keep-symbol
If one runs llvm-objcopy --strip-all --keep-symbol foo
and the symbol table indeed contains the symbol "foo"
then it should not be removed.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D47052

llvm-svn: 333008
2018-05-22 18:24:07 +00:00
Paul Semel 31a212d694 Revert "[llvm-objcopy] Add --strip-unneeded option"
There is a use after free I didn't see. Need to investigate.

This reverts commit f7624abeb1f0d012309baf2e78cf2499fbfe5e5f.

llvm-svn: 332925
2018-05-22 01:04:36 +00:00
Paul Semel 040df77ed6 [llvm-objcopy] Add --strip-unneeded option
This option removes symbols that are not needed by relocations.

Differential Revision: https://reviews.llvm.org/D46896

llvm-svn: 332915
2018-05-21 22:50:32 +00:00
Peter Collingbourne c5a9765cea LTO: Replace split dwarf implementation that uses objcopy with one that uses direct emission.
Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47091

llvm-svn: 332884
2018-05-21 20:26:49 +00:00
Jonas Devlieghere c111382aa8 [DebugInfo] Use absolute addresses in location lists
Rather than relying on the user to do the address calculating in
DW_AT_location we should just dump the absolute address.

rdar://problem/38513870

Differential revision: https://reviews.llvm.org/D47152

llvm-svn: 332873
2018-05-21 19:36:54 +00:00
Andrea Di Biagio cb1ed400a4 [llvm-mca] Removed an empty line generated by the timeline view. NFC.
Also, regenerate all tests.

llvm-svn: 332853
2018-05-21 17:11:56 +00:00
Andrea Di Biagio b5757abefb [X86][BtVer2] Add a 'J' prefix to the PRF/RCU defs. NFC
This is to keep the Jaguar model's naming convention. Processor resources all
have a 'J' prefix in the BtVer2 scheduling model.

llvm-svn: 332851
2018-05-21 16:30:26 +00:00
Nico Weber da5513b9c4 win: try to fix dia tests with newer msvc versions
llvm-svn: 332827
2018-05-21 02:09:57 +00:00
Simon Pilgrim 1273f4ad93 [X86] Add GPR<->XMM Schedule Tags
BtVer2 - fix NumMicroOp and account for the Lat+6cy GPR->XMM and Lat+1cy XMm->GPR delays (see rL332737)

The high number of MOVD/MOVQ equivalent instructions meant that there were a number of missed patterns in SNB/Znver1:
SNB - add missing GPR<->MMX costs (taken from Agner / Intel AOM)
Znver1 - add missing GPR<->XMM MOVQ costs (taken from Agner)

llvm-svn: 332745
2018-05-18 17:58:36 +00:00
Simon Pilgrim 007b50fd35 [X86][BtVer2] Improve simulation of (V)PINSR values
Include the 6cy delay transferring from the GPR to FPU.

llvm-svn: 332737
2018-05-18 17:09:41 +00:00
Simon Pilgrim 3ecb0b80f6 [X86][BtVer2] Partial vector stores (inc MMX) have a 2cy latency
llvm-svn: 332722
2018-05-18 14:22:22 +00:00
Simon Pilgrim c4b8d367a8 [X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecStore scheduler classes
Retag some instructions that were missed when we split off vector load/store/moves - MOVQ/MOVD etc.

Fixes BtVer2/SLM which have different behaviours for GPR stores.

llvm-svn: 332718
2018-05-18 14:08:01 +00:00
Simon Pilgrim d749b321b2 [X86][SSE] Ensure float load/stores use the WriteFLoad/WriteFStore scheduler classes
Retag some instructions that were missed when we split off vector load/store/moves - MOVSS/MOVSD/MOVHPD/MOVHPD/MOVLPD/MOVLPS etc.

Fixes BtVer2/SLM which have different behaviours for GPR stores.

llvm-svn: 332714
2018-05-18 13:13:59 +00:00
Simon Pilgrim e389ea0e3e [llvm-mca][X86] Add CMOV test files
llvm-svn: 332622
2018-05-17 16:29:12 +00:00
Simon Pilgrim b5741f5c3d [X86][BtVer2] ADC/SBB take 2cy on an ALU pipe, not 1cy like ADD/SUB
llvm-svn: 332616
2018-05-17 15:43:23 +00:00
Andrea Di Biagio 650b5fc6cb [llvm-mca] add flag -all-views and flag -all-stats.
Flag -all-views enables all the views.
Flag -all-stats enables all the views that print hardware statistics.

llvm-svn: 332602
2018-05-17 12:27:03 +00:00
Simon Pilgrim b4fd145fc3 [llvm-mca][X86] Add ADX test files
llvm-svn: 332595
2018-05-17 11:32:38 +00:00
Simon Pilgrim d5d77dcb46 [X86] Fix typo in instregex for CVTSI642SDrr
llvm-svn: 332510
2018-05-16 18:31:17 +00:00
Andrea Di Biagio 45ccdd1785 [llvm-mca] Regenerate tests after r332381 and r332361. NFC
llvm-svn: 332447
2018-05-16 10:12:06 +00:00
Jake Ehrlich e40398ad98 [llvm-objcopy] Add --only-keep-debug as a noop
This option just keeps being a problem and really needs to be implemented
in some fashion. Implementing it properly requires some kind of
"replaceSectionReference" method because all the existing links need to be
maintained. The desired behavior is just for allocated sections to become
NOBITS but actually implementing that is rather tricky due to the current
design of llvm-objcopy. However converting allocated sections to NOBITS is
just an optimization and not something debuggers need. Debuggers can debug
a stripped executable and take an unstripped executable for that stripped
executable as input. Additionally allocated sections account for a very
small part of debug binaries so this optimization is quite small. I propose
that for the time being we implement this as a NOP so that people can use
llvm-objcopy where they need to, just in a sub-optimal way.

This option has already blocked a lot of people and its currently blocking me.

llvm-svn: 332396
2018-05-15 20:53:53 +00:00
Martin Storsjo e241ce6f65 [llvm-rc] Add support for the optional CLASS statement for dialogs
Differential Revision: https://reviews.llvm.org/D46875

llvm-svn: 332386
2018-05-15 19:21:28 +00:00
Simon Pilgrim be9a206883 [X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classes
BtVer2 - Fixes schedules for (V)CVTPS2PD instructions

A lot of the Intel models still have too many InstRW overrides for these new classes - this needs cleaning up but I wanted to get the classes in first

llvm-svn: 332376
2018-05-15 17:36:49 +00:00
Simon Pilgrim 891ebcdbaa [X86] Split off F16C WriteCvtPH2PS/WriteCvtPS2PH scheduler classes
Btver2 - VCVTPH2PSYrm needs to double pump the AGU
Broadwell - missing VCVTPS2PH*mr stores extra latency

Allows us to remove the WriteCvtF2FSt conversion store class

llvm-svn: 332357
2018-05-15 14:12:32 +00:00
Paul Semel 5d97c823a4 [llvm-objcopy] Add --keep-symbol (-K) option
This option permits to explicitly keep the specified
symbol so that it doesn't get removed.

Differential Revision: https://reviews.llvm.org/D46819

llvm-svn: 332356
2018-05-15 14:09:37 +00:00
Pavel Labath 80827f10a1 Reapply "DWARFVerifier: Check "completeness" of .debug_names section"
This is a resubmit of r331868 (D46583), which was reverted due to
failures on the PS4 bot.

These have been resolved with r332246/D46748.

llvm-svn: 332349
2018-05-15 13:24:10 +00:00
Simon Pilgrim 2aa395abcf [llvm-mca][x86] Add F16C instruction tests
llvm-svn: 332347
2018-05-15 12:50:06 +00:00
Martin Storsjo 11adbacac8 [llvm-rc] Add support for parsing memory flags
Most of the handling is pretty straightforward; fetch the default
memory flags for the specific resource type before parsing the flags
and apply them on top of that, except that some flags imply others
and some flags clear more than one flag.

For icons and cursors, the flags set get passed on to all individual
single icon/cursor resources, while only some flags affect the icon/cursor
group resource.

For stringtables, the behaviour is pretty simple; the first stringtable
resource of a bundle sets the flags for the whole bundle.

The output of these tests match rc.exe byte for byte.

The actual use of these memory flags is deprecated and they have no
effect since Win16, but some resource script files may still happen
to have them in place.

Differential Revision: https://reviews.llvm.org/D46818

llvm-svn: 332329
2018-05-15 06:35:29 +00:00
Martin Storsjo 860e5fcdf4 [llvm-rc] Read the Planes/BitCount fields from BITMAPINFOHEADER for icons
Previously these fields were only read from this header for cursors,
while Planes was hardcoded to 1 for icons (with a comment that it was
unknown why this was needed) and BitCount was left at the value
read originally in the RESDIRENTRY.

This fixes the single byte that was differing for the icon/cursor test
compared to rc.exe.

This is based on research/testing by Nico Weber.

Differential Revision: https://reviews.llvm.org/D46816

llvm-svn: 332328
2018-05-15 06:35:20 +00:00
Martin Storsjo 5556841cd3 [llvm-rc] Add missing inputs for tag-icon-cursor.test.
This adds the missing input files used for this test, except for
the separate input files for specific error cases; matching
test input files were provided by Nico Weber.

The extra copying of files into the %t directory doesn't seem to
be necessary since that directory only ever is used for output here,
not for inputs.

Differential Revision: https://reviews.llvm.org/D46813

llvm-svn: 332297
2018-05-14 21:32:47 +00:00
Simon Pilgrim 5bd5e2fd3e [llvm-mca][X86] Add missing SSE4A test file
llvm-svn: 332270
2018-05-14 18:20:40 +00:00
Simon Pilgrim 228d24a2d6 [X86][BtVer2] Fix MMX/YMM integer vector nt store schedules
MMX was missing and YMM was tagged as a fp nt store

llvm-svn: 332269
2018-05-14 18:07:28 +00:00
Simon Pilgrim 4135de2e93 [llvm-mca][x86] Add scalar nt-store instruction tests
llvm-svn: 332262
2018-05-14 17:10:33 +00:00
Simon Pilgrim 7340d88740 [llvm-mca][x86] Add and/not/or/xor instruction tests
llvm-svn: 332257
2018-05-14 16:26:24 +00:00
Simon Pilgrim 661ae7778d [X86][BtVer2] Model ymm move as double pumped instructions
We still need to handle mmx/xmm moves as 'decode-only' no-pipe instructions

llvm-svn: 332109
2018-05-11 17:38:36 +00:00
Simon Pilgrim 706403bab8 [X86][MMX] Tag MMX Move/Load/Store as WriteVec schedule classes
Fixes an issue on SLM/Btver2 where we had instructions were being treated as scalar loads/stores

llvm-svn: 332104
2018-05-11 16:38:59 +00:00
Simon Pilgrim 032a01f74a [X86][SLM] Vector stores only use the MEC port.
Confirmed by both Agner and Intel's AOM - the IEC/FPC are not required for pure load/stores (even if its a partial update).

Can't fix WriteStore until all RMW instructions are cleaned up though....

llvm-svn: 332096
2018-05-11 15:16:15 +00:00
Simon Pilgrim 22dd72b995 [X86] Split WriteF/WriteVec Move/Load/Store scheduler classes by vector width
Fixes a SNB issue that was missing vlddqu/vmovntdqa ymm instructions

llvm-svn: 332094
2018-05-11 14:30:54 +00:00
Alexander Shaposhnikov 18b5fb7b84 [llvm-strip] Add support for -remove-section
This diff adds support for -remove-section to llvm-strip.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D46567

llvm-svn: 332081
2018-05-11 05:27:06 +00:00
Alexander Shaposhnikov 191913e3e7 [llvm-objcopy] Update remove-section.test
Verify that the input binary is not getting modified
and add an invocation which uses -remove-section instead of -R.

Test plan: make check-all

llvm-svn: 332078
2018-05-11 04:30:57 +00:00
Sam Clegg a5908009cd [WebAsembly] Update default triple in test files to wasm32-unknown-unkown.
Summary: The final -wasm component has been the default for some time now.

Subscribers: jfb, dschuff, jgravelle-google, eraman, aheejin, JDevlieghere, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D46342

llvm-svn: 332007
2018-05-10 17:49:11 +00:00
Simon Pilgrim 37fbb7f173 [X86][SNB] Fix typo in PEXTRDmr instregex, was missing VPEXTRDmr.
llvm-svn: 332002
2018-05-10 17:30:49 +00:00
Alexander Shaposhnikov af555fb4a3 [llvm-objcopy] Add tests for help messages
This diff slightly reorganizes the tests  and improves 
the test coverage of help messages / error reports.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D46589

llvm-svn: 331993
2018-05-10 15:56:04 +00:00
James Henderson a3acf99e59 [DWARF] Rework debug line parsing to use llvm::Error and callbacks
Reviewed by: dblaikie, JDevlieghere, espindola

Differential Revision: https://reviews.llvm.org/D44560

Summary:
The .debug_line parser previously reported errors by printing to stderr and
return false. This is not particularly helpful for clients of the library code,
as it prevents them from handling the errors in a manner based on the calling
context. This change switches to using llvm::Error and callbacks to indicate
what problems were detected during parsing, and has updated clients to handle
the errors in a location-specific manner. In general, this means that they
continue to do the same thing to external users. Below, I have outlined what
the known behaviour changes are, relating to this change.

There are two levels of "errors" in the new error mechanism, to broadly
distinguish between different fail states of the parser, since not every
failure will prevent parsing of the unit, or of subsequent unit. Malformed
table errors that prevent reading the remainder of the table (reported by
returning them) and other minor issues representing problems with parsing that
do not prevent attempting to continue reading the table (reported by calling a
specified callback funciton). The only example of this currently is when the
last sequence of a unit is unterminated. However, I think it would be good to
change the handling of unrecognised opcodes to report as minor issues as well,
rather than just printing to the stream if --verbose is used (this would be a
subsequent change however).

I have substantially extended the DwarfGenerator to be able to handle
custom-crafted .debug_line sections, allowing for comprehensive unit-testing
of the parser code. For now, I am just adding unit tests to cover the basic
error reporting, and positive cases, and do not currently intend to test every
part of the parser, although the framework should be sufficient to do so at a
later point.

Known behaviour changes:
  - The dump function in DWARFContext now does not attempt to read subsequent
  tables when searching for a specific offset, if the unit length field of a
  table before the specified offset is a reserved value.
  - getOrParseLineTable now returns a useful Error if an invalid offset is
  encountered, rather than simply a nullptr.
  - The parse functions no longer use `WithColor::warning` directly to report
  errors, allowing LLD to call its own warning function.
  - The existing parse error messages have been updated to not specifically
  include "warning" in their message, allowing consumers to determine what
  severity the problem is.
  - If the line table version field appears to have a value less than 2, an
  informative error is returned, instead of just false.
  - If the line table unit length field uses a reserved value, an informative
  error is returned, instead of just false.
  - Dumping of .debug_line.dwo sections is now implemented the same as regular
  .debug_line sections.
  - Verbose dumping of .debug_line[.dwo] sections now prints the prologue, if
  there is a prologue error, just like non-verbose dumping.

As a helper for the generator code, I have re-added emitInt64 to the
AsmPrinter code. This previously existed, but was removed way back in r100296,
presumably because it was dead at the time.

This change also requires a change to LLD, which will be committed separately.

llvm-svn: 331971
2018-05-10 10:51:33 +00:00
Douglas Yung 1d4c29c437 Fix tests added in r331924 so that they work on Windows.
The test needed to check for the optional executable extension (llvm-objcopy.EXE).

llvm-svn: 331952
2018-05-10 03:06:42 +00:00
Paul Semel 4246a462a3 [llvm-objcopy] Add --strip-symbol (-N) option
llvm-svn: 331924
2018-05-09 21:36:54 +00:00
Martin Storsjo 518b6c9882 [llvm-rc] Handle C preprocessor output
When preprocessing resource scripts (which can easily be done outside
of llvm-rc), included headers can leave behind C declarations (despite
preprocessing with -DRC_INVOKED), that can't be parsed by a resource
compiler.

This is handled in all of rc.exe, by parsing the preprocessor output
line markers and ignoring content from files named *.h and *.c,
documented at [1].

In addition to this filtering, strip out any other preprocessor directive
that is left behind (like pragmas) which also can't be handled by the
tokenizer.

The added test uses both standard #line markers (supported by rc.exe) and
GNU style extended line markers, thus this test doesn't pass with rc.exe,
but passes with GNU windres. (Windres on the other hand doesn't filter
out files named *.c, only *.h.)

Differential Revision: https://reviews.llvm.org/D46579

[1] https://msdn.microsoft.com/en-us/library/windows/desktop/aa381033(v=vs.85).aspx

llvm-svn: 331903
2018-05-09 18:21:03 +00:00
Martin Storsjo 7bc3c5822e [llvm-rc] Add support for the RCDATA resource type
This is the same as any other user defined resource, but with
a specific allocated resource type number.

Differential Revision: https://reviews.llvm.org/D46636

llvm-svn: 331902
2018-05-09 18:20:56 +00:00
Martin Storsjo c1a67857ba [llvm-rc] Allow -1 for control IDs in old style dialogs with 16 bit fields
-1 is commonly used as ID for controls that one don't want to
refer to later. For DIALOG resources, the IDs are 16 bit numbers,
and -1 gets interpreted as UINT32_MAX earlier, which then later is
too large to write into a uint16_t.

Differential Revision: https://reviews.llvm.org/D46506

llvm-svn: 331901
2018-05-09 18:20:49 +00:00
Pavel Labath e0207a60dd Revert "DWARFVerifier: Check "completeness" of .debug_names section"
The new verifier check has found an error in the
debug-names-name-collisions.ll test on the PS4 bot:

error: Name Index @ 0x0: Entry @ 0xdc: mismatched Name of DIE @ 0x23: index - _ZN3foo3fooE; debug_info - foo.

Reverting while I investigate whether this is a bug in the verifier or
the generator.

This reverts commit r331868.

llvm-svn: 331869
2018-05-09 12:26:19 +00:00
Pavel Labath 3280e0467f DWARFVerifier: Check "completeness" of .debug_names section
Summary:
This patch implements a check which makes sure all entries required by
the DWARF v5 specification are present in the Name Index. The algorithm
tries to follow the wording of Section 6.1.1.1 of the spec as closely as
possible.

The main deviation from it is that instead of a whitelist-based approach
in the spec "The name index must contain an entry for each debugging
information entry that defines a named subprogram, label, variable,
type, or namespace" I chose a blacklist-based one, where I consider
everything to be "in" and then remove the entries that don't make sense.
I did this because it has more potential for catching interesting cases
and the above is a bit vague (it uses plain words like "variable" and
"subprogram", but the rest of the section speaks about specific TAGs).

This approach has raised some interesting questions, the main one being
whether enumerator values should be indexed. The consensus seems to be
that they should, although it does not follow from section 6.1.1.1.
For the time being I made the verifier ignore these, as LLVM does not do
this yet, and I wanted to get a clean run when verifying generated debug
info.

Another interesting case was the DW_TAG_imported_declaration. It was not
immediately clear to me whether this should go in or not, but currently
it is not indexed, and (unlike the enumerators) in does not seem to cause
problems for LLDB, so I've also ignored it.

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46583

llvm-svn: 331868
2018-05-09 12:06:17 +00:00
Simon Pilgrim ab34aa8294 [X86] Cleanup WriteFStore/WriteVecStore schedules
MOVNTPD/MOVNTPS should be WriteFStore

Standardized BDW/HSW/SKL/SKX WriteFStore/WriteVecStore - fixes some missed instregex patterns. (V)MASKMOVDQU was already using the default, its costs gets increased but is still nowhere near the real cost of that nasty instruction....

llvm-svn: 331864
2018-05-09 11:01:16 +00:00
Martin Storsjo 284ab80f8d [COFF] Improve correctness of def parsing for GNU features
The operator == used for exporting a function with a different
name in the DLL compared to the name in the import library
(which is useful for adding linker level aliases for function
in the import library) is a feature distinct and different from
the operator = used for exporting a function with a different
name (both in import library and DLL) than in the implementation
producing the DLL.

When creating an import library using dlltool, from a def file that
contains forwards (Func = OtherDll.Func), this shouldn't affect the
produced import library, which should still behave just as if it
was a normal exported function.

This clears a lot of confusion and subtle misunderstandings, and
avoids a parameter that was used to avoid creating weak aliases
when invoked from lld. (This parameter was added previously due to
the existing conflation of the two features.)

Differential Revision: https://reviews.llvm.org/D46245

llvm-svn: 331859
2018-05-09 09:21:53 +00:00
Shiva Chen 2c864551df [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
In order to set breakpoints on labels and list source code around
labels, we need collect debug information for labels, i.e., label
name, the function label belong, line number in the file, and the
address label located. In order to keep these information in LLVM
IR and to allow backend to generate debug information correctly.
We create a new kind of metadata for labels, DILabel. The format
of DILabel is

!DILabel(scope: !1, name: "foo", file: !2, line: 3)

We hope to keep debug information as much as possible even the
code is optimized. So, we create a new kind of intrinsic for label
metadata to avoid the metadata is eliminated with basic block.
The intrinsic will keep existing if we keep it from optimized out.
The format of the intrinsic is

llvm.dbg.label(metadata !1)

It has only one argument, that is the DILabel metadata. The
intrinsic will follow the label immediately. Backend could get the
label metadata through the intrinsic's parameter.

We also create DIBuilder API for labels to be used by Frontend.
Frontend could use createLabel() to allocate DILabel objects, and use
insertLabel() to insert llvm.dbg.label intrinsic in LLVM IR.

Differential Revision: https://reviews.llvm.org/D45024

Patch by Hsiangkai Wang.

llvm-svn: 331841
2018-05-09 02:40:45 +00:00
Martin Storsjo 818bd56809 [llvm-rc] Add support for all missing dialog controls
Differential Revision: https://reviews.llvm.org/D46507

llvm-svn: 331808
2018-05-08 20:55:58 +00:00
Max Moroz 0c5b602015 [Coverage] Take filenames into account when loading function records.
Summary:
Don't skip functions with the same name but from different files.

That change makes it possible to generate code coverage reports from
different binaries compiled from different sources even if there are functions
with non-unique names. Without that change, code coverage for such functions is
missing except of the first function processed.

Reviewers: vsk, morehouse

Reviewed By: vsk

Subscribers: llvm-commits, kcc

Differential Revision: https://reviews.llvm.org/D46478

llvm-svn: 331801
2018-05-08 19:26:51 +00:00
Alexander Shaposhnikov b07c22b081 [llvm-objcopy] Fix exit code
Set the exit code to 1 if no arguments are specified.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D46547

llvm-svn: 331776
2018-05-08 17:12:54 +00:00
Simon Pilgrim 2864b46469 [X86] Split off WriteIMul64 from WriteIMul schedule class (PR36931)
This fixes a couple of BtVer2 missing instructions that weren't been handled in the override.

NOTE: There are still a lot of overrides that still need cleaning up!
llvm-svn: 331770
2018-05-08 14:55:16 +00:00
Simon Pilgrim 739d1a68aa [llvm][x86] SandyBridge/IvyBridge don't support BMI1/BMI2
llvm-svn: 331769
2018-05-08 14:20:25 +00:00
Simon Pilgrim 2580554333 [X86] Split WriteIDiv into div/idiv 8/16/32/64 implementations (PR36930)
I've created the necessary classes but there are still a lot of overrides that need cleaning up.

NOTE: The Znver1 model was missing some div/idiv variants in the instregex patterns and wasn't setting the resource cycles at all in the overrides.
llvm-svn: 331767
2018-05-08 13:51:45 +00:00
Simon Pilgrim 4283924e08 [llvm-mca][x86] Add div/idiv, mul/imul and inc/dec/neg/nop instruction tests
llvm-svn: 331765
2018-05-08 13:30:58 +00:00
Martin Storsjo 4021cee996 [llvm-rc] Don't strictly require quotes around external file names
Regardless of what docs may say, existing resource files in the
wild can use this syntax.

Rename a file used in an existing test, to make it usable for unquoted
paths.

Differential Revision: https://reviews.llvm.org/D46511

llvm-svn: 331747
2018-05-08 08:47:37 +00:00
Simon Pilgrim 061096d2c2 [llvm-mca][x86] Remove addsubpd from SSE2 tests
llvm-svn: 331678
2018-05-07 21:10:48 +00:00
Simon Pilgrim 1233e1234a [X86] Split WriteFAdd/WriteFCmp/WriteFMul schedule classes
Split to support single/double for scalar, XMM and YMM/ZMM instructions - removing InstrRW overrides for these instructions.

Fixes Atom ADDSUBPD instruction and reclassifies VFPCLASS as WriteFCmp which is closer in behaviour.

llvm-svn: 331672
2018-05-07 20:52:53 +00:00
Martin Storsjo 577b981748 [llvm-rc] Implement the BITMAP resource type
Differential Revision: https://reviews.llvm.org/D46509

llvm-svn: 331670
2018-05-07 20:27:37 +00:00
Martin Storsjo 9410276cf7 [llvm-rc] Allow optional commas between the string table index and value
This form is even used in one of the examples at
https://msdn.microsoft.com/en-us/library/windows/desktop/aa381050(v=vs.85).aspx.

Differential Revision: https://reviews.llvm.org/D46508

llvm-svn: 331669
2018-05-07 20:27:28 +00:00
Martin Storsjo 28ae894a1d [llvm-rc] Exclude padding from sizes in versioninfo resources
Normally when writing something that requires padding, we first
measure the length of the written payload data, then write
padding if necessary.

For a recursive structure like versioninfo, this means that the
padding is excluded from the size of the inner element, but
included in the size of the enclosing block.

Rc.exe excludes the final padding (but not the padding of earlier
children) from all levels of the hierarchy.

To achieve this, don't pad after each block or value, but only
before starting the next one. We still pad after completing the
toplevel versioninfo resource, so this won't affect other resource
types.

Differential Revision: https://reviews.llvm.org/D46510

llvm-svn: 331668
2018-05-07 20:27:23 +00:00
Alexander Shaposhnikov cca6998504 [tools] Introduce llvm-strip
llvm-strip is supposed to be a drop-in replacement for binutils strip.
To start the ball rolling this diff adds the initial bits for llvm-strip,
more features will be added incrementally over time.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D46407

llvm-svn: 331663
2018-05-07 19:32:09 +00:00
Simon Pilgrim e480ed0b9f [X86][AVX2] Tag VPMOVSX/VPMOVZX ymm instructions as WriteShuffle256
These are more like cross-lane shuffles than regular shuffles - we already do this for AVX512 equivalents.

Differential Revision: https://reviews.llvm.org/D46229

llvm-svn: 331659
2018-05-07 18:25:19 +00:00
Simon Pilgrim 763bf12085 [X86][Znver1] Remove WriteFMul/WriteFRcp InstRW overrides/aliases.
Fixes x87 schedules to more closely match Agner - AMD doesn't tend to "special case" x87 instructions as much as Intel.

llvm-svn: 331645
2018-05-07 16:34:26 +00:00
Simon Pilgrim ac5d0a31ef [X86] Split WriteFDiv schedule classes to support single/double scalar, XMM and YMM/ZMM instructions.
This removes all InstrRW overrides for these instructions - some x87 overrides remain but most use default (and realistic) values.

llvm-svn: 331643
2018-05-07 16:15:46 +00:00
Simon Pilgrim f3ae50fca2 [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classes
WriteFRcp/WriteFRsqrt are split to support scalar, XMM and YMM/ZMM instructions.

WriteFSqrt is split into single/double/long-double sizes and scalar, XMM, YMM and ZMM instructions.

This removes all InstrRW overrides for these instructions.

NOTE: There were a couple of typos in the Znver1 model - notably a 1cy throughput for SQRT that is highly unlikely and doesn't tally with Agner.

NOTE: I had to add Agner's numbers for several targets for WriteFSqrt80.
llvm-svn: 331629
2018-05-07 11:50:44 +00:00
Simon Pilgrim 0e51a125ea [X86] Add WriteEMMS scheduler class
Filled in the missing values from Btver2 SoG or Agner

llvm-svn: 331546
2018-05-04 18:16:13 +00:00
Simon Pilgrim be51b20127 [X86] Add SchedWriteFRnd fp rounding scheduler classes
Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions.

Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA.

llvm-svn: 331515
2018-05-04 12:59:24 +00:00
Simon Pilgrim 0aed731516 [X86][Znver1] Use SchedAlias to tag microcoded scheduler classes
Avoids extra entries in the class tables.

Found a typo that missed the MMX_PHSUBSW instruction.

llvm-svn: 331488
2018-05-03 22:12:23 +00:00
Martin Storsjo e3b437935f [llvm-rc] Default to writing the output next to the input, if no output is specified
This matches what rc.exe does if no output is specified.

Differential Revision: https://reviews.llvm.org/D46239

llvm-svn: 331403
2018-05-02 21:15:24 +00:00
Martin Storsjo ca16978967 [llvm-cvtres] Allow parameters preceded by '-' in addition to '/'
The real cvtres.exe also allows parameters in either form.

Differential Revision: https://reviews.llvm.org/D46358

llvm-svn: 331402
2018-05-02 21:15:13 +00:00
Paul Semel 41695f8e73 [llvm-objcopy] Add --discard-all (-x) option
llvm-svn: 331400
2018-05-02 20:19:22 +00:00
Paul Semel 2c0510f040 [llvm-objcopy] Add --weaken option
llvm-svn: 331397
2018-05-02 20:14:49 +00:00
Martin Storsjo d1d046aa32 [llvm-rc] Add rudimentary support for codepages
Only support UTF-8 (since LLVM contains UTF-8 parsing support
already, and the code even does that already) and Windows-1252
(where most code points has the same value in unicode). Keep the
existing default as only allowing ASCII input.

Using the option type JoinedOrSeparate, since the real rc.exe
handles options in this form, even if llvm-rc uses Separate for
other similar existing options.

Rename the struct SearchParams to WriterParams since it's now used
for more than just include paths.

Add a missing getResourceTypeName method to the BundleResource class,
to fix error printing from within STRINGTABLE resources (used in
tests).

Differential Revision: https://reviews.llvm.org/D46238

llvm-svn: 331391
2018-05-02 19:43:44 +00:00
Simon Pilgrim 350c22c587 [X86][SNB] Fix scheduling of MMX integer multiply instructions.
The entries were being bound to the wrong class.

llvm-svn: 331388
2018-05-02 19:26:14 +00:00
Clement Courbet a1a3095d88 [X86] Fix scheduling info for (V?)SQRTPDm on silvermont.
https://reviews.llvm.org/D46356

llvm-svn: 331356
2018-05-02 13:46:14 +00:00
Sam Clegg 7381216710 [WebAssembly] llvm-readobj: display symbols names in relocations
Differential Revision: https://reviews.llvm.org/D46296

llvm-svn: 331279
2018-05-01 16:35:16 +00:00
Jonas Devlieghere 4bbcb5ab04 [DebugInfo] Prevent infinite recursion for malformed DWARF
This prevents infinite recursion in DWARFDie::findRecursively for
malformed DWARF where a DIE references itself.

This fixes PR36257.

Differential revision: https://reviews.llvm.org/D43092

llvm-svn: 331200
2018-04-30 17:02:41 +00:00
Andrea Di Biagio e047d3529b [llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.
This fixes PR37293.

We can have scheduling classes with no write latency entries, that still consume
processor resources. We don't want to treat those instructions as zero-latency
instructions; they still have to be issued to the underlying pipelines, so they
still consume resource cycles.

This is likely to be a regression which I have accidentally introduced at
revision 330807. Now, if an instruction has a non-empty set of write processor
resources, we conservatively treat it as a normal (i.e. non zero-latency)
instruction.

llvm-svn: 331193
2018-04-30 15:55:04 +00:00
Andrea Di Biagio 77bd1c748a [llvm-mca] Regenerate test Atom/resources-sse3.s. NFC
Before this change, it wrongly specified -mcpu=slm instead of -mcpu=atom.

llvm-svn: 331170
2018-04-30 12:13:04 +00:00
Andrea Di Biagio e9384eb13b [llvm-mca] Support for in-order CPU for -instruction-tables testing.
Added Intel Atom tests to verify that the tool correctly generates instruction
tables even if the CPU is in-order.

Fixes PR37282.

llvm-svn: 331169
2018-04-30 12:05:34 +00:00
Simon Pilgrim 8962c344f9 [llvm-mca][X86] Add BT resource tests to all models
llvm-svn: 331144
2018-04-29 15:45:31 +00:00
Simon Pilgrim 2d569361fc [llvm-mca][X86] Add add/adc + sub/sbb resource tests to all models
llvm-svn: 331140
2018-04-29 11:03:25 +00:00
Simon Pilgrim 318e9d39ab [llvm-mca][X86] Add double shift resource tests to all relevant models
llvm-svn: 331109
2018-04-28 15:18:49 +00:00
Simon Pilgrim 4d0187c893 [llvm-mca][X86] Add shift/rotate resource tests to all relevant models
I intend to add further instruction tests to the resources-x86_64.s test file as required, but this initial commit is to help remove a load of unnecessary InstRW overrides in a future patch

llvm-svn: 331108
2018-04-28 14:56:18 +00:00
Paul Semel 3a8a56b8b7 [llvm-objcopy] Add --weaken-symbol (-W) option
llvm-svn: 331070
2018-04-27 19:16:27 +00:00
Paul Semel ee5be798da [llvm-objcopy] Add --globalize-symbol option
llvm-svn: 331068
2018-04-27 19:09:44 +00:00
Sam Clegg e0658119ba typo
llvm-svn: 331006
2018-04-27 00:17:24 +00:00
Sam Clegg d5504a0a62 [WebAssembly] Section symbols must have local binding
Summary: Also test for symbols information in test/MC/WebAssembly/debug-info.ll.

Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D46160

llvm-svn: 331005
2018-04-27 00:17:21 +00:00
Alexander Shaposhnikov 40e9bdf9af [llvm-objcopy] Implement --redefine-sym option
This diff implements --redefine-sym option 
for changing the name of a symbol.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D46029

llvm-svn: 330973
2018-04-26 18:28:17 +00:00
Sam Clegg 6bb5a41f99 [WebAssembly] Add version to object file metadata
Summary: See https://github.com/WebAssembly/tool-conventions/issues/54

Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D46069

llvm-svn: 330969
2018-04-26 18:15:32 +00:00
Paul Semel b492494c0f [llvm-objcopy] Add --localize-symbol option
llvm-svn: 330963
2018-04-26 17:44:43 +00:00
Sam Clegg 8c4b0ce2b1 [WebAssembly] objdump: Don't assume all relocations have symbols
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D46134

llvm-svn: 330959
2018-04-26 17:05:04 +00:00
Sam Clegg f676cdd515 [WebAssembly] Implement getRelocationValueString()
And use it in llvm-objdump.

Differential Revision: https://reviews.llvm.org/D46092

llvm-svn: 330957
2018-04-26 16:41:51 +00:00
Simon Pilgrim 7574ffd7bc [llvm-mca][X86] Updated fma3 tests after rL330820
llvm-svn: 330822
2018-04-25 13:19:04 +00:00
Andrea Di Biagio 93c49d5e58 [llvm-mca] Default to the native host cpu if flag -mcpu is not specified.
llvm-svn: 330809
2018-04-25 10:18:25 +00:00
Simon Pilgrim 27bc83e228 [X86] Split off PHMINPOSUW to their own schedule class
This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default. 

llvm-svn: 330756
2018-04-24 18:49:25 +00:00
Sam Clegg 6f08c84ae5 [WebAssembly] Use section index in relocation section header
Rather than referring to sections my their code, use the
absolute index of the target section within the module.

See https://github.com/WebAssembly/tool-conventions/issues/52

Differential Revision: https://reviews.llvm.org/D45980

llvm-svn: 330749
2018-04-24 18:11:36 +00:00
Simon Pilgrim f0945aa0e0 [X86][F16C] Add WriteCvtF2FSt scheduling class
Fixes the classification of VCVTPS2PHmr/VCVTPS2PHYmr which were tagged as WriteCvtF2FLd_WriteRMW (PR36887)

llvm-svn: 330737
2018-04-24 16:43:07 +00:00
Simon Pilgrim 828ef9e013 [X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latencies
These are stores, not loads, so don't need to account for load latency.

llvm-svn: 330735
2018-04-24 16:26:51 +00:00
Simon Pilgrim f35b8ac196 [X86][IVB] Add F16C resource tests.
Note this is IvyBridge (which shares the model) NOT SandyBridge.

llvm-svn: 330734
2018-04-24 16:22:59 +00:00
Andrea Di Biagio 0626864fa4 [llvm-mca] Default the output asm dialect used by the instruction printer to the input asm dialect.
The instruction printer used by llvm-mca to generate the performance report now
defaults the output assembly format to the format used for the input assembly
file.

On x86, the asm format can be either AT&T or Intel, depending on the
presence/absence of directive `.intel_syntax`.

Users can still specify a different assembly dialect with the command line flag
-output-asm-variant=<uint>.

llvm-svn: 330733
2018-04-24 16:19:08 +00:00
Simon Pilgrim 16299273d0 [X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides.
llvm-svn: 330720
2018-04-24 14:47:11 +00:00
Simon Pilgrim f7d2a93d5f [X86] Add vector element insertion/extraction scheduler classes
Split off pinsr/pextr and extractps instructions.

(Mostly) fixes PR36887.

Note: It might be worth adding a WriteFInsertLd class as well in the future.

Differential Revision: https://reviews.llvm.org/D45929

llvm-svn: 330714
2018-04-24 13:21:41 +00:00
Alexander Shaposhnikov d6884795d0 Recommit "[llvm-objcopy] Switch over to using TableGen for parsing arguments"
Add explicit dependency on ObjcopyTableGen 
and rerun the tests on Windows. 
I will double-check the build bots 
and revert this commit if necessary.

llvm-svn: 330685
2018-04-24 05:43:32 +00:00
Adrian Prantl bbe980dfe1 Fix computeSymbolSizes SEGFAULT on invalid file
We use llvm-symbolizer in some production systems, and we run it
against all possibly related files, including some that are not
ELF. We noticed that for some of those invalid files, llvm-symbolizer
would crash with SEGFAULT. Here is an example of such a file.

It is due to that in computeSymbolSizes, a loop uses condition

  for (unsigned I = 0, N = Addresses.size() - 1; I < N; ++I) {

where if Addresses.size() is 0, N would overflow and causing the loop
to access invalid memory.

Instead of patching the loop conditions, the commit makes so that the
function returns early if Addresses is empty.

Validated by checking that llvm-symbolizer no longer crashes.

Patch by Teng Qin!

Differential Revision: https://reviews.llvm.org/D44285

llvm-svn: 330610
2018-04-23 16:08:01 +00:00
Simon Pilgrim 87ba905fe9 [llvm-mca][X86] Add BMI/LZCNT/POPCNT resource tests to all relevant models
The SandyBridge BMI tests are actually run on IvyBridge as that's the first lowest CPU that actually support the ISAs (but still use the SandyBridge model).

llvm-svn: 330556
2018-04-22 20:42:24 +00:00
Simon Pilgrim 96855ec39e [X86] Remove unnecessary WriteFVarBlend/WriteVarBlend InstRW overrides.
This also fixes some of the ReadAfterLd issues due to InstRW.

llvm-svn: 330544
2018-04-22 14:43:12 +00:00
Simon Pilgrim 5e9f1da0cd [llvm-mca][X86] Add POPCNT resource test
llvm-svn: 330540
2018-04-22 09:58:00 +00:00
Simon Pilgrim e25aa02bc4 [llvm-mca][X86] Add AVX2 resource tests
llvm-svn: 330512
2018-04-21 16:12:42 +00:00
Simon Pilgrim d73bd154d9 [llvm-mca][X86] Add SSE resource tests to all models
llvm-svn: 330506
2018-04-21 14:16:57 +00:00
Simon Pilgrim 26178d4336 [llvm-mca][X86] Add MMX resource tests
llvm-svn: 330502
2018-04-21 11:28:59 +00:00
Simon Pilgrim 1264066cd7 [llvm-mca][X86] Add X87 resource tests
llvm-svn: 330499
2018-04-21 10:36:19 +00:00
Simon Pilgrim 1803bfb75f [llvm-mca][X86] Add MMX/SSE/AES/CLMUL resource SandyBridge tests
llvm-svn: 330486
2018-04-20 22:04:11 +00:00
Alexander Shaposhnikov 52db4335b3 [llvm-objcopy] Fix sh_link
This diff fixes sh_link for various types of sections 
(i.e. for SHT_ARM_EXIDX, SHT_HASH). In particular, this change enables us
to use llvm-objcopy with clang -gsplit-dwarf for the target android-arm.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D45851

llvm-svn: 330478
2018-04-20 20:46:04 +00:00
Douglas Yung 51db3abac8 Fix test by allowing it to accept an upper or lower case letter as the first character.
Windows for some reason uses a lower case letter, while linux uses upper case.

llvm-svn: 330438
2018-04-20 15:23:57 +00:00
Florian Hahn 3085cdc99e Require asserts for stats-file-option tests.
llvm-svn: 330417
2018-04-20 11:21:13 +00:00
Florian Hahn d4332eb3b7 [LTO] Add stats-file option to LTO/Config.h.
This patch adds a StatsFile option to LTO/Config.h and updates both
LLVMGold and llvm-lto2 to set it.

Reviewers: MatzeB, tejohnson, espindola

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D45531

llvm-svn: 330411
2018-04-20 10:18:36 +00:00
Simon Pilgrim 0a6bfb1843 [llvm-mca][X86] Add prefetch instruction resource tests
llvm-svn: 330371
2018-04-19 22:11:58 +00:00
Simon Pilgrim 7209117868 [llvm-mca][FMA] Add FMA resource tests
llvm-svn: 330366
2018-04-19 21:32:22 +00:00
Simon Pilgrim 4a486c13fa [llvm-mca][X86] Add resource test for every out-of-order scheduler model
I've copied and regenerated a resource file from btver2 to every x86 scheduler model supported by llvm-mca so we have at least some basic coverage.

For most this has been the avx1 tests, but for silvermont I've used sse42 as thats the latest it supports.

More will be added later.

llvm-svn: 330352
2018-04-19 18:08:10 +00:00
Francis Visoiu Mistrih dca79d2867 [llvm-objdump] Remove test object file
Forgot to remove it from the previous commit.

llvm-svn: 330343
2018-04-19 17:05:03 +00:00
Francis Visoiu Mistrih 1834682b97 [llvm-objdump] Print "..." instead of random data for virtual sections
When disassembling with -D, skip virtual sections by printing "..." for
each symbol.

This patch also implements `MachOObjectFile::isSectionVirtual`.

Test case comes from:

```
.zerofill __DATA,__common,_data64unsigned,472,3
```

Differential Revision: https://reviews.llvm.org/D45824

llvm-svn: 330342
2018-04-19 17:02:57 +00:00
Simon Pilgrim f209321d61 [llvm-mca][X86] Add mmx instruction to btver2 resource tests
Useful to see scheduler class deltas against xmm equivalents

llvm-svn: 330335
2018-04-19 15:09:46 +00:00
Simon Pilgrim c310bfa193 [llvm-mca][X86] Add mmx versions of SSSE3 instructions
Move PABS instructions incorrectly tested under SSE2 

llvm-svn: 330295
2018-04-18 20:47:48 +00:00
Teresa Johnson b214af26b3 [gold] Add support for optimization remarks
Summary:
Adds support for LTO opt remarks (optionally with hotness) to
gold-plugin.

Reviewers: anemet

Subscribers: fhahn, mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D45752

llvm-svn: 330252
2018-04-18 13:25:23 +00:00
Greg Bedwell 90d141a295 [UpdateTestChecks] Add update_mca_test_checks.py script
This script can be used to regenerate tests in the
test/tools/llvm-mca directory (PR36904).

Regenerated a number of tests using the pattern: test/tools/llvm-mca/*/*/*.s

Differential Revision: https://reviews.llvm.org/D45369

llvm-svn: 330246
2018-04-18 10:27:45 +00:00
Craig Topper e56a2fc5e7 [X86] Add separate scheduling class for PSADBW instruction.
llvm-svn: 330204
2018-04-17 19:35:19 +00:00
Pavel Labath 54d736c416 [test] Avoid spurious failure in debug-names-find.s. NFC.
Have llvm-dwarfdump take input from stdin to avoid leaking the host paths into
the tests, causing nondeterministic failures.

llvm-svn: 330121
2018-04-16 11:16:41 +00:00
Sean Fertile eaa1607b48 Add PPC64_GLINK dynamic tag.
Add support for the PPC64_GLINK dynamic tag which is used in the ElfV2 abi.

Differential Revision: https://reviews.llvm.org/D45574

llvm-svn: 330038
2018-04-13 16:42:48 +00:00
Andrea Di Biagio c752616f30 [llvm-mca] Ensure that instructions with a schedule read-advance are always issued in the right order.
Normally, the Scheduler prioritizes older instructions over younger instructions
during the instruction issue stage. In one particular case where a dependent
instruction had a schedule read-advance associated to one of the input operands,
this rule was not correctly applied.

This patch fixes the issue and adds a test to verify that we don't regress that
particular case.

llvm-svn: 330032
2018-04-13 15:19:07 +00:00
Yunlian Jiang bd200b9ff6 Enable debug fission for thinLTO linked via gold-plugin
Summary: This enables debug fission on implicit ThinLTO when linked with gold. It will put the .dwo files in a directory specified by user. 

Reviewers: tejohnson, pcc, dblaikie

Reviewed By: pcc

Subscribers: JDevlieghere, mehdi_amini, inglorion

Differential Revision: https://reviews.llvm.org/D44792

llvm-svn: 329988
2018-04-13 05:03:28 +00:00
Brian Gesiak d0d2ce9425 Let llvm-diff correctly deal with Undef/ConstantAggregateZero/ConstantVector/IndirectBr
Summary:
llvm-diff incorrectly reports that there's a diff when input IR contains undef/zeroinitializer/constantvector/indirectbr.
(This happens even if two identical files are given, e.g. `llvm-diff x.ll x.ll`)

This is fix to the bug report https://bugs.llvm.org/show_bug.cgi?id=33623 .



Reviewers: dexonsmith, rjmccall

Reviewed By: rjmccall

Subscribers: chenwj, mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D34856

llvm-svn: 329957
2018-04-12 21:28:04 +00:00
Sam Clegg 9745afa674 [WebAssembly] libObject: Don't include the name the size of custom sections
Differential Revision: https://reviews.llvm.org/D45579

llvm-svn: 329947
2018-04-12 20:31:12 +00:00
Jake Ehrlich a8c689e70c Revert "[llvm-objcopy] Switch over to using TableGen for parsing arguments"
TableGen seems to work differently on windows. I'll need to revert this

This reverts commit 7a153ddea067b24da59f6a66c733d79205969501.

llvm-svn: 329867
2018-04-12 00:40:50 +00:00
Jake Ehrlich cafa11289a [llvm-objcopy] Switch over to using TableGen for parsing arguments
Swithces from using the command line library to using TableGen. This will allow
llvm-strip to exist and allow refinements of the command line syntax.

Differential Revision: https://reviews.llvm.org/D44236

llvm-svn: 329863
2018-04-11 23:37:03 +00:00
Andrea Di Biagio f41ad5c59e [llvm-mca] Renamed BackendStatistics to RetireControlUnitStatistics.
Also, removed flag -verbose in favor of flag -retire-stats.

llvm-svn: 329794
2018-04-11 12:12:53 +00:00
Andrea Di Biagio 1cc29c045e [llvm-mca] Move the logic that prints scheduler statistics from BackendStatistics to its own view.
Added flag -scheduler-stats to print scheduler related statistics.

llvm-svn: 329792
2018-04-11 11:37:46 +00:00
Andrea Di Biagio 821f650bba [llvm-mca] Move the logic that prints dispatch unit statistics from BackendStatistics to its own view.
This patch moves the logic that collects and analyzes dispatch events to the
DispatchStatistics view.

Added flag -dispatch-stats to print statistics related to the dispatch logic.

llvm-svn: 329708
2018-04-10 14:55:14 +00:00
Aaron Smith 13cb6be05a [pdbutil] Print the checksum hex string when using the '-lines' option
llvm-svn: 329707
2018-04-10 14:47:12 +00:00
Andrea Di Biagio 074cef3dfb [llvm-mca] Increase the default number of iterations to 100.
llvm-svn: 329694
2018-04-10 12:50:03 +00:00
Alexandre Ganea 037d3b20d3 [llvm-ar] Temporarily make the tool case detection test Windows-only to fix the build (introduced in r329658)
llvm-svn: 329683
2018-04-10 10:26:23 +00:00
Andrea Di Biagio c9f409eb6f Reapply "[llvm-mca] Do not separate iterations with a newline in the timeline view."
This reapplies r329403 with a fix for the floating point rounding issue.

llvm-svn: 329680
2018-04-10 09:55:33 +00:00
Alexandre Ganea 76a0154ce5 [llvm-ar] Fix lib.exe detection when running within MSVC toolchain
Differential Revision: https://reviews.llvm.org/D44808

llvm-svn: 329658
2018-04-10 01:50:25 +00:00
Andrea Di Biagio c65901282b [llvm-mca] Add the ability to mark regions of code for analysis (PR36875)
This patch teaches llvm-mca how to parse code comments in search for special
"markers" used to select regions of code.

Example:

# LLVM-MCA-BEGIN My Code Region
  ....
# LLVM-MCA-END

The MCAsmLexer now delegates to an object of class MCACommentParser (i.e. an
AsmCommentConsumer) the parsing of code comments to search for begin/end code
region markers.

A comment starting with substring "LLVM-MCA-BEGIN" marks the beginning of a new
region of code.  A comment starting with substring "LLVM-MCA-END" marks the end
of the last region.

This implementation doesn't allow regions to overlap. Each region can have a
optional description; internally, each region is identified by a range of source
code locations (SMLoc).

MCInst objects are added to a region R only if the source location for the
MCInst is in the range of locations specified by R.

By default, the tool allocates an implicit "Default" code region which contains
every source location.  See new tests llvm-mca-marker-*.s for a few examples.

A new Backend object is created for every region. So, the analysis is conducted
on every parsed code region.  The final report is the union of the reports
generated for every code region.  Note that empty regions are skipped.

Special "[#] Code Region - ..." strings are used in the report to mark the
portion which is specific to a code region only. For example, see
llvm-mca-markers-5.s.

Differential Revision: https://reviews.llvm.org/D45433

llvm-svn: 329590
2018-04-09 16:39:52 +00:00
Max Moroz 4220f89107 [llvm-cov] Implement -ignore-filename-regex= option for excluding source files.
Summary:
The option is helpful for large projects where it's not feasible to specify sources which
user would like to see in the report. Instead, it allows to black-list specific sources via
regular expressions (e.g. now it's possible to skip all files that have "test" in its name).

This also partially fixes https://bugs.llvm.org/show_bug.cgi?id=34277

Reviewers: vsk, morehouse, liaoyuke

Reviewed By: vsk

Subscribers: kcc, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D43907

llvm-svn: 329581
2018-04-09 15:20:35 +00:00
Hans Wennborg 6400c03e6a Revert r329403 "[llvm-mca] Do not separate iterations with a newline in the timeline view."
This made AArch64/CortexA57/direct-branch.s fail on Windows, e.g.
http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/11251

> Also, update a few tests to minimize the diff in D45369.
> No functional change intended.

llvm-svn: 329569
2018-04-09 13:53:41 +00:00
Jonas Devlieghere 79766820a3 [dsymutil] Don't try to load Swift ASTs as objects.
With the threading refactoring, loading of object files happens before
checking whether we're dealing with a swift AST. While that's not an
issue per se, it causes a warning to be printed:

  warning: /path/to/a.swiftmodule: The file was not recognized as a valid object file
  note: while processing /path/to/a.swiftmodule

This suppresses the warning by checking for a Swift AST before
attempting to load is as an object file.

rdar://39240444

llvm-svn: 329553
2018-04-09 09:09:59 +00:00
Jonas Devlieghere c226a7b820 [dsymutil] Don't crash on empty CU
Add some additional checks so we don't crash on empty compile units.

llvm-svn: 329537
2018-04-08 17:35:17 +00:00
Simon Pilgrim 86588fc809 [X86][Btver2] Add vector extract costs
llvm-svn: 329524
2018-04-08 11:26:26 +00:00
Andrea Di Biagio 85b8138bc6 [llvm-mca] Do not separate iterations with a newline in the timeline view.
Also, update a few tests to minimize the diff in D45369.
No functional change intended.

llvm-svn: 329403
2018-04-06 15:30:02 +00:00
Pavel Labath c9f07b06a1 DWARFVerifier: validate information in name index entries
Summary:
This patch add checks to verify that the information in the name index
entries is consistent with the debug_info section. Specifically, we
check that entries point to valid DIEs, and their names, tags, and
compile units match the information in the debug_info sections.

These checks are only run if the previous checks did not find any errors
in the name index headers. Attempting to proceed with the checks anyway
would likely produce a lot of spurious errors and the verification code
would need to be very careful to avoid crashing.

I also add a couple of more checks to the abbreviation-validation code
to verify that some attributes are always present (an index without a
DW_IDX_die_offset attribute is fairly useless).

The entry verification works only on indexes without any type units - I
haven't attempted to extend it to type units, as we don't even have a
DWARF v5-compatible type unit generator at the moment.

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45323

llvm-svn: 329392
2018-04-06 13:34:12 +00:00
Pavel Labath 54ca2d688a [debug_loc] Fix typo in DWARFExpression constructor
Summary:
The positions of the DwarfVersion and AddressSize arguments were
reversed, which caused parsing for dwarf opcodes which contained
address-size-dependent operands (such as DW_OP_addr). Amusingly enough,
none of the address-size asserts fired, as dwarf version was always 4,
which is a valid address size.

I ran into this when constructing weird inputs for the DWARF verifier. I
I add a test case as hand-written dwarf -- I am not sure how to trigger
this differently, as having a DW_OP_addr inside a location list is a
fairly non-standard thing to do.

Fixing this error exposed a bug in the debug_loc.dwo parser, which was
always being constructed with an address size of 0. I fix that as well
by following the pattern in the non-dwo parser of picking up the address
size from the first compile unit (which is technically not correct, but
probably good enough in practice).

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45324

llvm-svn: 329381
2018-04-06 08:49:57 +00:00
Andrea Di Biagio c74ad502ce [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca.
This patch adds the ability to describe properties of the hardware retire
control unit.

Tablegen class RetireControlUnit has been added for this purpose (see
TargetSchedule.td).

A RetireControlUnit specifies the size of the reorder buffer, as well as the
maximum number of opcodes that can be retired every cycle.

A zero (or negative) value for the reorder buffer size means: "the size is
unknown". If the size is unknown, then llvm-mca defaults it to the value of
field SchedMachineModel::MicroOpBufferSize.  A zero or negative number of
opcodes retired per cycle means: "there is no restriction on the number of
instructions that can be retired every cycle".

Models can optionally specify an instance of RetireControlUnit. There can only
be up-to one RetireControlUnit definition per scheduling model.

Information related to the RCU (RetireControlUnit) is stored in (two new fields
of) MCExtraProcessorInfo.  llvm-mca loads that information when it initializes
the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp).

This patch fixes PR36661.

Differential Revision: https://reviews.llvm.org/D45259

llvm-svn: 329304
2018-04-05 15:41:41 +00:00