Commit Graph

11 Commits

Author SHA1 Message Date
Aditya Nandakumar 2980b01995 [GISel]: Pattern matchers for GFSUB, GFNEG
https://reviews.llvm.org/D47547

Add matching templates for G_FSUB, and G_FNEG.

Reviewed by: aemerson.

llvm-svn: 333685
2018-05-31 19:30:01 +00:00
Aditya Nandakumar b1c467dbe7 [GISel] Refactor MachineIRBuilder to allow transformations while
building.

https://reviews.llvm.org/D45067

This change attempts to do two things:
1) It separates out the state that is stored in the
MachineIRBuilder(InsertionPt, MF, MRI, InsertFunction etc) into a
separate object called MachineIRBuilderState.
2) Add the ability to constant fold operations while building instructions
(optionally). MachineIRBuilder is now refactored into a MachineIRBuilderBase
which contains lots of non foldable build methods and their implementation.
Instructions which can be constant folded/transformed are now in a class
called FoldableInstructionBuilder which uses CRTP to use the implementation
of the derived class for buildBinaryOps. Additionally buildInstr in the derived
class can be used to implement other kinds of transformations.

Also because of separation of state, given a MachineIRBuilder in an API,
if one wishes to use another MachineIRBuilder, a new one can be
constructed from the state locally. For eg,

void doFoo(MachineIRBuilder &B) {
  MyCustomBuilder CustomB(B.getState());
  // Use CustomB for building.
}

reviewed by : aemerson

llvm-svn: 329596
2018-04-09 17:30:56 +00:00
Aditya Nandakumar b808e3ad8b [GISel]: Fix incorrect type used in Pattern Match for ICst
getConstantVRegVal() returns int64_t but we use uint64_t.

llvm-svn: 327461
2018-03-13 23:21:13 +00:00
Aditya Nandakumar 91fc4e0949 [GISel]: Add helpers for easy building G_FCONSTANT along with matchers
Added helpers to build G_FCONSTANT, along with matching ConstantFP and
unit tests for the same.

Sample usage.

auto MIB = Builder.buildFConstant(s32, 0.5); // Build IEEESingle
For Matching the above

const ConstantFP* Tmp;
mi_match(DstReg, MRI, m_GFCst(Tmp));

https://reviews.llvm.org/D44128
reviewed by: volkan

llvm-svn: 327152
2018-03-09 17:31:51 +00:00
Volkan Keles 2bc42e90ed GlobalISel: IRTranslate llvm.fabs.* intrinsic
Summary:
Fabs is a common floating-point operation, especially for some expansions. This patch adds
a new generic opcode for llvm.fabs.* intrinsic in order to avoid building/matching this intrinsic.

Reviewers: qcolombet, aditya_nandakumar, dsanders, rovka

Reviewed By: aditya_nandakumar

Subscribers: kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D43864

llvm-svn: 326749
2018-03-05 22:31:55 +00:00
Aditya Nandakumar cf85f31172 [GISel]: Fix base case for m_any_of PatternMatcher.
The base case for any_of was incorrectly returning true. Also add test
case which uses m_any_of(preds...) where none of the predicates are
true.

llvm-svn: 325848
2018-02-23 01:01:59 +00:00
Aditya Nandakumar bab2d3e2b9 [GISel]: Add pattern matchers for G_BITCAST/PTRTOINT/INTTOPTR
Adds pattern matchers for the above along with unit tests for the same.
https://reviews.llvm.org/D43479

llvm-svn: 325542
2018-02-19 23:11:53 +00:00
Volkan Keles 02bb1747a3 GlobalISel: Add templated functions and pattern matcher support for some more opcodes
Summary:
This patch adds templated functions to MachineIRBuilder for some opcodes
and adds pattern matcher support for G_AND and G_OR.

Reviewers: aditya_nandakumar

Reviewed By: aditya_nandakumar

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D43309

llvm-svn: 325162
2018-02-14 19:58:36 +00:00
Aditya Nandakumar 6250b18831 [GISel]: Add Pattern Matcher for G_FMUL.
https://reviews.llvm.org/D43206

llvm-svn: 325044
2018-02-13 20:09:13 +00:00
Puyan Lotfi 43e94b15ea Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00
Aditya Nandakumar 2036f44654 Add support for pattern matching MachineInsts.
https://reviews.llvm.org/D42439

Add Instcombine like matchers for MachineInstructions. There are only
globalISel matchers for now.

llvm-svn: 323400
2018-01-25 02:53:06 +00:00