Commit Graph

24590 Commits

Author SHA1 Message Date
Jack Carter f9f753c2ea Mips ELF: Mark object file as ABI compliant
When producing objects that are abi compliant we are 
marking neither the object file nor the assembly file
correctly and thus generate warnings. 

We need to set the EF_CPIC flag in the ELF header when
generating direct object.

Note that the warning is only generated when compiling without PIC.

When compiling with clang the warning will be suppressed by supplying:

 -Wa,-mno-shared -Wa,-call_nonpic

Also the following directive should also be added:

	.option	pic0

when compiling without PIC,  This eliminates the need for supplying:

  -mno-shared -call_nonpic

on the assembler command line.

Patch by Douglas Gilmore

llvm-svn: 184220
2013-06-18 19:47:15 +00:00
David Blaikie 141b2acb9d Reduce indentation.
llvm-svn: 184213
2013-06-18 18:03:17 +00:00
Stefanus Du Toit 8811ad4f81 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.

llvm-svn: 184207
2013-06-18 17:08:10 +00:00
Amaury de la Vieuville eac0bad084 ARM: fix literal load with positive offset encoding
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly

This patch also makes the assembler look at the .w/.n specifier for
loads.

llvm-svn: 184182
2013-06-18 08:13:05 +00:00
Amaury de la Vieuville aa7fdf8741 ARM: add operands pre-writeback variants when needed
llvm-svn: 184181
2013-06-18 08:12:51 +00:00
Amaury de la Vieuville 4d3e3f279e ARM: fix thumb literal loads decoding
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one

llvm-svn: 184180
2013-06-18 08:03:06 +00:00
Amaury de la Vieuville e2bb1d150c ARM: thumb stores cannot use PC as dest register
llvm-svn: 184179
2013-06-18 08:02:56 +00:00
Bill Wendling bc07a8900c Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.

No functionality change intended.

llvm-svn: 184175
2013-06-18 07:20:20 +00:00
Bill Wendling b7b1681157 Remove dead prototype.
llvm-svn: 184173
2013-06-18 06:24:14 +00:00
Vincent Lejeune 41d4cf26b4 R600: PV stores Reg id, not index
llvm-svn: 184117
2013-06-17 20:16:40 +00:00
Vincent Lejeune 8bd10421ec R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.
Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 184116
2013-06-17 20:16:26 +00:00
David Blaikie b735b4d6db DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

llvm-svn: 184067
2013-06-16 20:34:27 +00:00
David Blaikie 0252265be0 Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions
Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This
reduces the complexity of debug info handling down to two
representations of values (reg+offset and frame index+offset) rather
than three or four.

Ideally we could ensure that frame indicies had been eliminated by the
time we reached an assembly or dwarf generation, but I haven't spent the
time to figure out where the FIs are leaking through into that & whether
there's a good place to convert them. Some FI+offset=>reg+offset
conversion is done (see PrologEpilogInserter, for example) which is
necessary for some SelectionDAG assumptions about registers, I believe,
but it might be possible to make this a more thorough conversion &
ensure there are no remaining FIs no matter how instruction selection
is performed.

llvm-svn: 184066
2013-06-16 20:34:15 +00:00
Andrew Trick 40c4f38071 Support BufferSize on ProcResGroup for unified MOp schedulers.
And add Sandybridge/Haswell resource buffers.

llvm-svn: 184034
2013-06-15 04:50:06 +00:00
Andrew Trick 18dc3da855 Update machine models. Specify buffer sizes for OOO processors.
llvm-svn: 184033
2013-06-15 04:50:02 +00:00
Andrew Trick de2109eb4c Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

llvm-svn: 184032
2013-06-15 04:49:57 +00:00
Tom Stellard 371573448c R600: Add SI load support for v[24]i32 and store for v2i32
Also add a seperate vector lit test file, since r600 doesn't seem to handle
v2i32 load/store yet, but we can test both for SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 184021
2013-06-15 00:09:31 +00:00
Tom Stellard ecf9d86404 R600: Use correct encoding for Vertex Fetch instructions on Cayman
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184016
2013-06-14 22:12:30 +00:00
Tom Stellard 6aa0d5578d R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman
We were using RAT_INST_STORE_RAW, which seemed to work, but the docs
say this instruction doesn't exist for Cayman, so it's probably safer
to use a documented instruction instead.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184015
2013-06-14 22:12:24 +00:00
Tom Stellard d99b7932ae R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184014
2013-06-14 22:12:19 +00:00
Tom Stellard 3d0823f1cd R600: Move instruction encoding definitions into a separate .td file
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184013
2013-06-14 22:12:09 +00:00
Amaury de la Vieuville e804ae1188 ARM: fix thumb coprocessor instruction with pre-writeback disassembly
was        stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!

llvm-svn: 183975
2013-06-14 11:21:35 +00:00
Benjamin Kramer b289319fb8 X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equivalent.
Give it the right register format so we can also emit it when AVX is enabled.

llvm-svn: 183971
2013-06-14 09:31:41 +00:00
JF Bastien 18db1f2f1a Enable FastISel on ARM for Linux and NaCl, not MCJIT
This is a resubmit of r182877, which was reverted because it broken
MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only
enabled for iOS. I've CC'ed people from the original review and revert.

FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl, but not MCJIT.

Thumb2 support needs a bit more work, mainly around register class
restrictions.

The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.

The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.

The test changes are straightforward, similar to:
  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.

I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0
and all the tests pass. All the tests also pass on x86 make check-all. I
also re-ran the check-all tests that failed on ARM, and they all seem to
pass.

llvm-svn: 183966
2013-06-14 02:49:43 +00:00
Tom Stellard adba083bc2 R600: Don't try to fix reg class when copying IMPLICIT_DEF to a register
The test case for this is way too complex to be useful as a lit test,
and I was unable to reduce it.

https://bugs.freedesktop.org/show_bug.cgi?id=65438

llvm-svn: 183937
2013-06-13 20:14:00 +00:00
Benjamin Kramer c4d547d3ae Mips: Remove global set.
Backends shouldn't retain any global state. No functionality change.

llvm-svn: 183927
2013-06-13 19:06:52 +00:00
Amaury de la Vieuville bd2b610eba ARM: fix B decoding
llvm-svn: 183914
2013-06-13 16:41:55 +00:00
Amaury de la Vieuville 231ca2bdc3 ARM: fix t2am_imm8_offset operand printing for imm=#-0
llvm-svn: 183913
2013-06-13 16:40:51 +00:00
Benjamin Kramer af6c3b7002 X86: Make the cmov aliases work with intel syntax too.
llvm-svn: 183907
2013-06-13 15:45:24 +00:00
David Blaikie c2467c4e9b Revert r183854 (PPC: Fix switch warnings from r183841)
Now that the PRED_BAD has been removed, this is failing the Clang
-Werror build due to -Wcovered-switch-default.

llvm-svn: 183863
2013-06-12 20:57:32 +00:00
Bill Schmidt 4fcb8c260e [PowerPC] Remove PRED_BAD from PPC::Predicate enumeration.
I'm taking David Blaikie's suggestion to use an
Optional<PPC::Predicate> return value instead.  That's the right
solution for this problem.  Thanks for pointing out that possibility!

llvm-svn: 183858
2013-06-12 20:22:24 +00:00
Bill Schmidt 31c60f740e [PowerPC] Fix switch warnings from r183841.
Introducing PRED_BAD caused some unexpected warnings that are now
suppressed.

llvm-svn: 183854
2013-06-12 19:20:32 +00:00
Bill Schmidt 230b451389 [PowerPC] Expose some calling convention functions in PPCISelLowering.h.
This is a preparatory patch for fast-isel support.  The instruction
selector will need to access some functions in PPCGenCallingConv.inc,
which in turn requires several helper functions to be defined.  These
are currently defined near the only use of PCCGenCallingConv.inc,
inside PPCISelLowering.cpp.  This patch moves the declaration of the
functions into the associated header file to provide the needed
visibility.

No functional change intended.

llvm-svn: 183844
2013-06-12 16:39:22 +00:00
Bill Schmidt 6207a4b7dd Add artificial PRED_BAD to PPC::Predicate enumeration.
Allows returning a PPC::Predicate from a function with a no-predicate
value possible.  Preparatory patch for fast-isel on PPC64 ELF.  No
behavioral change intended.

llvm-svn: 183841
2013-06-12 15:14:42 +00:00
Ulrich Weigand 32d725b80a [MC/DWARF] Support .debug_frame / .debug_line code alignment factors
I've been comparing the object file output of LLVM's integrated
assembler against the external assembler on PowerPC, and one
area where differences still remain are in DWARF sections.

In particular, the GNU assembler generates .debug_frame and
.debug_line sections using a code alignment factor of 4, since
all PowerPC instructions have size 4 and must be aligned to a
multiple of 4.  However, current MC code hard-codes a code
alignment factor of 1.

This patch changes this by adding a "minimum instruction alignment"
data element to MCAsmInfo and using this as code alignment factor.

This requires passing a MCContext into MCDwarfLineAddr::Encode
and MCDwarfLineAddr::EncodeAdvanceLoc.  Note that one caller,
MCDwarfLineAddr::Write, didn't actually have that information
available.  However, it turns out that this routine is in fact
never used in the whole code base, so the patch simply removes
it.  If it turns out to be needed again at a later time, it
could be re-added with an updated interface.

llvm-svn: 183834
2013-06-12 14:46:54 +00:00
Patrik Hagglund 0cc888b786 Fix gcc -flto build, by adding LLVM_ATTRIBUTE_USED to
LLVMX86CompilationCallback2, called from inline asm.

llvm-svn: 183824
2013-06-12 08:45:39 +00:00
Eric Christopher 5331f0eeb8 Correct the def registers for the 8bit x86 divide instructions to
match the comments and what the instruction actually does. Noticed
on inspection.

llvm-svn: 183809
2013-06-11 23:41:44 +00:00
Eric Christopher 8f6a083be7 Use the Copy we defined above here.
llvm-svn: 183808
2013-06-11 23:41:41 +00:00
Akira Hatanaka f5288c26de Fix CMakeLists.
llvm-svn: 183804
2013-06-11 22:36:30 +00:00
Akira Hatanaka 5c50a16ee0 [mips] Add an IR transformation pass that optimizes calls to sqrt.
The pass emits a call to sqrt that has attribute "read-none". This call will be
converted to an ISD::FSQRT node during DAG construction, which will turn into
a mips native sqrt instruction.
 

llvm-svn: 183802
2013-06-11 22:21:44 +00:00
JF Bastien 3c6bb8e19f ARM FastISel fix sext/zext fold
Sign- and zero-extension folding was slightly incorrect because it wasn't checking that the shift on extensions was zero. Further, I recently added AND rd, rn, #255 as a form of 8-bit zero extension, and failed to add the folding code for it.

This patch fixes both issues.

This patch fixes both, and the test should remain the same:
  test/CodeGen/ARM/fast-isel-fold.ll

llvm-svn: 183794
2013-06-11 22:13:46 +00:00
Akira Hatanaka 4be04b139b [mips] Use function TargetInstrInfo::getRegClass.
No functionality changes.

llvm-svn: 183767
2013-06-11 18:48:16 +00:00
Benjamin Kramer 193960c822 R600: Make helper functions static.
llvm-svn: 183744
2013-06-11 13:32:25 +00:00
NAKAMURA Takumi 4d5ee8046f Rework r183728, suppress assert(0) for now. Its behavior depends on assertions on win32 hosts.
FIXME: Introduce yet another checker but assert(0).
llvm-svn: 183736
2013-06-11 10:01:42 +00:00
Mihai Popa c1d119ed6e It adds support for negative zero offsets for loads and stores.
Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.

llvm-svn: 183734
2013-06-11 09:48:35 +00:00
Mihai Popa 1c7be576c5 This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
llvm-svn: 183733
2013-06-11 09:39:51 +00:00
Amaury de la Vieuville 064546cbfe ARM: Enforce decoding rules for VLDn instructions
llvm-svn: 183731
2013-06-11 08:14:14 +00:00
Amaury de la Vieuville 53ff029d62 ARM: Fix STREX/LDREX reecoding
The decoded MCInst wasn't reencoded as the same instruction

llvm-svn: 183729
2013-06-11 08:03:20 +00:00
NAKAMURA Takumi 1ab3650ec0 Tweak a couple of tests on win32 hosts with +Asserts.
- Don't use assert(0), or tests may pass or fail according to assertions.
  - For now, The tests are marked as XFAIL for win32 hosts.

FIXME: Could we avoid XFAIL to specify triple in the RUN lines?
llvm-svn: 183728
2013-06-11 06:52:58 +00:00
NAKAMURA Takumi 76380ab4c0 ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().
FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk.

llvm-svn: 183727
2013-06-11 06:52:43 +00:00