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Author SHA1 Message Date
Stepan Dyatkovskiy f80f9513ce Fix for 5.5 Parameter Passing --> Stage C: 
-- C.4 and C.5 statements, when NSAA is not equal to SP.
 -- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a
    variadic procedure.

Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are
some exceptions in AAPCS.
1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated
   CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs.
2. Check that for VA functions all params uses GPRs and then stack.
   No exceptions, no CPRCs here.

llvm-svn: 180011
 2013-04-22 13:06:52 +00:00
Stephen Lin b8bd232a3d Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). 
llvm-svn: 179925
 2013-04-20 05:14:40 +00:00
Chad Rosier 1ec8e404fc Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all 
registers.  Previously, the register we being marked as implicitly defined, but
not killed.  In some cases this would cause the register scavenger to spill a
dead register.

Also, use an empty register mask to simplify the logic and to reduce the memory
footprint.
rdar://12592448

llvm-svn: 167499
 2012-11-06 23:05:24 +00:00
Manman Ren d6c8270eaa ARM: enable struct byval for AAPCS-VFP. 
This change is to be enabled in clang.

rdar://9877866

llvm-svn: 161789
 2012-08-13 21:22:50 +00:00
Manman Ren e201e27eb1 ARM: enable struct byval for AAPCS. 
This change is to be enabled in clang.

rdar://9877866
PR://13350

llvm-svn: 161693
 2012-08-10 20:39:38 +00:00
Eric Christopher b3322364e4 Add support for the ARM GHC calling convention, this patch was in 3.0, 
but somehow managed to be dropped later.

Patch by Karel Gardas.

llvm-svn: 161226
 2012-08-03 00:05:53 +00:00
Jay Foad 08a0598cd4 Remove unused CCIfSubtarget. 
llvm-svn: 154921
 2012-04-17 11:29:05 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Jakob Stoklund Olesen fdbb12b235 Implement ARMBaseRegisterInfo::getCallPreservedMask(). 
Move ARM callee-saved lists into ARMCallingConv.td.

llvm-svn: 148357
 2012-01-17 23:09:00 +00:00
Chad Rosier 5de1bea5c9 Enable support for returning i1, i8, and i16. Nothing special todo as it's the 
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047
 2011-11-08 00:03:32 +00:00
Chad Rosier fa75530ff0 Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well. 
llvm-svn: 144021
 2011-11-07 21:43:40 +00:00
Chad Rosier f0055f61fb Allow i1 to be promoted to i32 for ARM APCS calling convention. 
llvm-svn: 143755
 2011-11-05 00:02:56 +00:00
Stuart Hastings 45fe3c38c5 ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569> 
llvm-svn: 129858
 2011-04-20 16:47:52 +00:00
Stuart Hastings 67c5c3e939 Support for byval parameters on ARM. Will be enabled by a forthcoming 
patch to the front-end.  Radar 7662569.

llvm-svn: 126655
 2011-02-28 17:17:53 +00:00
Evan Cheng 08dd8c8295 Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now. 
llvm-svn: 117119
 2010-10-22 18:23:05 +00:00
Chris Lattner 72a364c107 fix emacs language spec's, patch by Edmund Grimley-Evans! 
llvm-svn: 111241
 2010-08-17 16:20:04 +00:00
Rafael Espindola 027d5bcf89 Fix eabi calling convention when a 64 bit value shadows r3. 
Without this what was happening was:

* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong

llvm-svn: 110446
 2010-08-06 15:35:32 +00:00
Rafael Espindola d90d169f9d Correctly align double arguments in the stack. 
llvm-svn: 85235
 2009-10-27 14:09:44 +00:00
Anton Korobeynikov 22ef75155e Missed pieces for ARM HardFP ABI. 
Patch by Sandeep Patel!

llvm-svn: 78225
 2009-08-05 19:04:42 +00:00
Bob Wilson 2e076c4e02 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919
 2009-06-22 23:27:02 +00:00
Anton Korobeynikov a8fd40b50a Address review comments: add 3 ARM calling conventions. 
Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.

llvm-svn: 73530
 2009-06-16 18:50:49 +00:00
Anton Korobeynikov 5b1b5b2a8a Typo 
llvm-svn: 73098
 2009-06-08 22:59:50 +00:00
Anton Korobeynikov 77d1943637 The attached patches implement most of the ARM AAPCS-VFP hard float 
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

llvm-svn: 73095
 2009-06-08 22:53:56 +00:00
Bob Wilson e666cc5206 Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and 
the stack.  Patch by Sandeep Patel.

llvm-svn: 72106
 2009-05-19 10:02:36 +00:00
Bob Wilson 62d47d2361 Remove unnecessary references to f32 types. After specifying that f32 
should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.

llvm-svn: 69973
 2009-04-24 16:55:25 +00:00
Bob Wilson ea09d4aca8 Clean up formatting, remove trailing whitespace, fix comment typos and 
punctuation.  No functional changes.

llvm-svn: 69378
 2009-04-17 20:35:10 +00:00
Bob Wilson a4c2290e5f Use CallConvLower.h and TableGen descriptions of the calling conventions 
for ARM.  Patch by Sandeep Patel.

llvm-svn: 69371
 2009-04-17 19:07:39 +00:00