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3 Commits

Author SHA1 Message Date
Benjamin Kramer ef479ea854 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
 2012-05-29 19:05:25 +00:00
Chris Lattner f7f59b15aa These tests used intrinsics with the wrong prototype. They weren't caught because 
the old verifier just checked that something "was a pointer", but not that the pointee
was correct.

llvm-svn: 157544
 2012-05-27 19:35:41 +00:00
Craig Topper d4e1894ec1 Add SSE4A MOVNTSS/MOVNTSD instructions. 
llvm-svn: 156281
 2012-05-07 05:36:19 +00:00