Commit Graph

370 Commits

Author SHA1 Message Date
Jaydeep Patil 7b531c1a11 [LLDB][MIPS] Using enum instead of a constant to fetch PC and CAUSE registers.
SUMMARY:
    Using enum instead of a constant to fetch PC and CAUSE registers.

llvm-svn: 254590
2015-12-03 06:41:24 +00:00
Abhishek Aggarwal 296e063d8f PTRACE ABI to read FXSAVE area for 32-bit inferior
Summary:
 - Problem occurs when:
    -- 32-bit inferiors run on x86_32 machine and
       the architecture doesn't have AVX feature

    -- This causes FPRType to be set to eFPRTypeFXSAVE

    -- PTRACE_GETFPREGS was being used to read FXSAVE area

    -- For 32-bit inferiors running on x86_32 machine,
       PTRACE_GETFPREGS reads FSAVE area and not FXSAVE area

 - Changed ptrace API to PTRACE_GETREGSET for 32-bit inferiors
    -- This reads FPR data in FXSAVE format.
    -- For 64-bit inferiors, no change has been made.

 - Modified XFAIL for TestReturnValue.py
    -- Earlier, this test was passing for Linux OS
    -- Now, it passes for Android OS as well

Change-Id: Ieed72bc969b79516fc7b263b32493aa1e7a1a2ac
Signed-off-by: Abhishek Aggarwal <abhishek.a.aggarwal@intel.com>

Reviewers: ovyalov, jingham, lldb-commits, tberghammer, labath

Subscribers: jevinskie, labath, tberghammer, danalbert

Differential Revision: http://reviews.llvm.org/D15042

llvm-svn: 254499
2015-12-02 09:40:17 +00:00
Sagar Thakur d4eb7cc3f3 [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS
This patch will clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS. The problem was that while emulating instructions, old and new pc values would have garbage value in their upper 32 bits. Therefore checking if pc was changed (old_pc == new_pc) would always return false, because of which pc was not getting updated.

/* If we haven't changed the PC, change it here */
if (old_pc == new_pc)
{
    new_pc += 4;
    Context context;
        return false;
}

Reviewers: tberghammer, clayborg
Subscribers: dsanders, lldb-commits, mohit.bhakkad, bhushan, jaydeep, nitesh.jain
Differential: http://reviews.llvm.org/D14633
llvm-svn: 254379
2015-12-01 05:44:18 +00:00
Tamas Berghammer b4e95a50d7 Add 64/128 bit arm neon register definitions on linux
Differential revision: http://reviews.llvm.org/D14985

llvm-svn: 254152
2015-11-26 15:02:31 +00:00
Mohit K. Bhakkad 5a998ed7a6 [LLDB][MIPS] Getting 0 index for H/W watchpoint is not necessarily an error
Reviewers: jaydeep.
Subscribers: bhushan, sagar, nitesh.jain, lldb-commits.
Differential Revision: http://reviews.llvm.org/D14860

llvm-svn: 253864
2015-11-23 12:19:59 +00:00
Omair Javaid f24741d9dc Fix for AArch64 watchpoint cache corruption in case of ptrace failure
Same fix has been submitted for Arm.

Review can be found here:

Differential revision: http://reviews.llvm.org/D14051

llvm-svn: 252298
2015-11-06 12:56:34 +00:00
Omair Javaid d5510d1e5c Fix for Arm watchpoint cache corruption in case of ptrace failure
Differential revision: http://reviews.llvm.org/D14051

llvm-svn: 251386
2015-10-27 05:56:56 +00:00
Omair Javaid 4aa984c1a2 Corrects return values and typos in Arm watchpoint code
This is just a trivial patch that corrects a couple of return value account to function's return type.
Also corrects typo in hardware breakpoint handler.

llvm-svn: 251269
2015-10-25 23:18:35 +00:00
Tamas Berghammer ce26b7a6ee Fix arm lldb-server on aarch64 device
* Use PTRACE_GETVFPREGS/PTRACE_SETVFPREGS to access the floating point
  registers instead of the old PTRACE_GETFPREGS/PTRACE_SETFPREGS. The
  new call is available since armv5.
* Work around a kernel issue in PTRACE_POKEUSER with reading out the full
  register set, modifying the neccessary value and then writing it back.

llvm-svn: 251111
2015-10-23 13:36:31 +00:00
Omair Javaid 5cf948d299 Fix for random watchpoint testsuite failures on AArch64 targets.
This patch corrects the number of bytes of debug register resources which are written while installing or removing a breakpoint using ptrace interface on arm64 targets.

Differential revision: http://reviews.llvm.org/D12522

llvm-svn: 250700
2015-10-19 14:54:33 +00:00
Sagar Thakur b997792cc6 [LLDB][MIPS] Use the correct ptrace buffer for writing register value for o32 applications
For o32 applications on mips we were getting segmentation fault while launching lldb-server because of overwritting stack when using elf_gregset_t in DoWriteRegisterValue.
We are now using the GPR_mips_linux buffer in DoWriteRegisterValue as done in DoReadRegisterValue also, which solves the above issue.

llvm-svn: 250696
2015-10-19 11:21:20 +00:00
Tamas Berghammer 1fa5c4b944 Fix cast in arm watchpoint handling code
We had an incorrect sign extension when castion from a pointer to an
lldb::addr_t what broke the watchpoint hit detection on arm.

llvm-svn: 250180
2015-10-13 16:48:04 +00:00
Abhishek Aggarwal b352a1c88f X86: Change FTAG register size in FXSAVE structure
Summary:
 - Changed from 16 bits to 8 bits for Intel Architecture
    -- FXSAVE structure now conforms with the layout of FXSAVE
       area specified by IA Architecture Software Developer Manual

 - Modified Linux and FreeBSD specific files to support this change
    -- MacOSX already uses 8 bits for ftag register

 - Modified TestRegisters.py and a.cpp:
    -- Change allows 8 bit comparison of ftag values

    -- Change resolves Bug 24733:
       Removed XFAIL for Clang as the test works and passes for
       Clang compiler as well

    -- Change provides a Generic/Better way of testing Bug 24457
       and Bug 25050 by using 'int3' inline assembly in inferior

Signed-off-by: Abhishek Aggarwal <abhishek.a.aggarwal@intel.com>

Reviewers: ovyalov, jingham, clayborg

Subscribers: tfiala, emaste

Differential Revision: http://reviews.llvm.org/D13587

llvm-svn: 250022
2015-10-12 09:57:00 +00:00
Sagar Thakur b8862c0107 [LLDB][MIPS] Fix gp register value for o32 applications on 64-bit target
GP registers for o32 applications were always giving zero value because SetType() on the RegisterValue was causing the accessor functions to pickup the value from m_scalar of RegisterValue which is zero.
In this patch byte size and byte order of register value is set at the time of setting the value of the register.

llvm-svn: 249020
2015-10-01 15:05:31 +00:00
Jason Molenda 63bd0db071 Clean up register naming conventions inside lldb.
"gcc" register numbers are now correctly referred to as "ehframe"
register numbers.  In almost all cases, ehframe and dwarf register
numbers are identical (the one exception is i386 darwin where ehframe
regnums were incorrect).

The old "gdb" register numbers, which I incorrectly thought were
stabs register numbers, are now referred to as "Process Plugin"
register numbers.  This is the register numbering scheme that the
remote process controller stub (lldb-server, gdbserver, core file
support, kdp server, remote jtag devices, etc) uses to refer to the
registers.  The process plugin register numbers may not be contiguous
- there are remote jtag devices that have gaps in their register
numbering schemes.

I removed all of the enums for "gdb" register numbers that we had
in lldb - these were meaningless - and I put LLDB_INVALID_REGNUM
in all of the register tables for the Process Plugin regnum slot.

This change is almost entirely mechnical; the one actual change in
here is to ProcessGDBRemote.cpp's ParseRegisters() which parses the
qXfer:features:read:target.xml response.  As it parses register
definitions from the xml, it will assign sequential numbers as the
eRegisterKindLLDB numbers (the lldb register numberings must be
sequential, without any gaps) and if the xml file specifies register
numbers, those will be used as the eRegisterKindProcessPlugin
register numbers (and those may have gaps).  A J-Link jtag device's
target.xml does contain a gap in register numbers, and it only 
specifies the register numbers for the registers after that gap.
The device supports many different ARM boards and probably selects
different part of its register file as appropriate.

http://reviews.llvm.org/D12791
<rdar://problem/22623262> 

llvm-svn: 247741
2015-09-15 23:20:34 +00:00
Tamas Berghammer c40e7b1769 Fix the handling of FPR offsets in Linux arm/aarch64 register contexts
Differential revision: http://reviews.llvm.org/D12636

llvm-svn: 246959
2015-09-07 10:11:23 +00:00
Abhishek Aggarwal 7f658edd61 Bug 24457 - X87 FPU Special Purpose Registers
Summary:
  - For 'register read --all' command on x86_64-Linux Platform:

      -- Provide correct values of X87 FPU Special Purpose Registers
      -- Both 32-bit & 64-bit inferiors give correct values on this
         Platform

  - Added a Test Vector:
      -- To verify the expected behaviour of the command

Signed-off-by: Abhishek Aggarwal <abhishek.a.aggarwal@intel.com>

Reviewers: ashok.thirumurthi, granata.enrico, tfiala, clayborg

Differential Revision: http://reviews.llvm.org/D12592

llvm-svn: 246955
2015-09-07 07:40:16 +00:00
Bruce Mitchener db25a7a245 [cmake] Remove LLVM_NO_RTTI.
Summary:
This doesn't exist in other LLVM projects any longer and doesn't
do anything.

Reviewers: chaoren, labath

Subscribers: emaste, tberghammer, lldb-commits, danalbert

Differential Revision: http://reviews.llvm.org/D12586

llvm-svn: 246749
2015-09-03 08:46:55 +00:00
Pavel Labath 7a9495bcd5 [NativeProcessLinux] Fix detach of multithreaded inferiors
When detaching, we need to detach from all threads of the inferior and not just the main one.
Without this, a multi-threaded inferior would usually crash once the server exits.

llvm-svn: 246549
2015-09-01 15:00:51 +00:00
Pavel Labath 86852d3676 [NativeProcessLinux] Fix assertion failure when killing a process
Linux sometimes sends us a PTRACE_EVENT_EXIT when an inferior process gets a SIGKILL. This can be
confusing, since normally we don't expect any events when the inferior is stopped. This commit
adds code to handle this situation (resume the thread and let it exit normally) and avoid an
assertion failure in ResumeThread().

llvm-svn: 246539
2015-09-01 10:59:36 +00:00
Mohit K. Bhakkad 16ad032183 [LLDB][MIPS] Aligning code with rL245831
Reviewers: jaydeep
Subscribers: lldb-commits.
Differential Revision: http://reviews.llvm.org/D12427

llvm-svn: 246293
2015-08-28 12:08:26 +00:00
Omair Javaid 3a56363aec Error checking correction in AArch64 hardware watchpoint code
Differential Revision: http://reviews.llvm.org/D12328

llvm-svn: 246045
2015-08-26 18:23:27 +00:00
Omair Javaid 2441aecd1e Adds support for hardware watchpoints on Arm targets.
http://reviews.llvm.org/D9703

This updated patches correct problems in arm hardware watchpoint support patch posted earlier.

This patch has been tested on samsung chromebook (ARM - Linux) and PandaBoard using basic watchpoint test application.

Also it was tested on Nexus 7 Android device.

On chromebook linux we are able to set and clear all types of watchpoints but on android we end up getting a watchpoint packet error because we are not able to call hardware watchpoint ptrace functions successfully.

llvm-svn: 245961
2015-08-25 18:22:04 +00:00
Sagar Thakur 3024117757 Fix build on mips
Setting and getting register values as bytes instead of depending on the 128 bit integer support in register value.
This patch will fix the build failure in the release branch.

Reviewers: tberghammer, clayborg, hans
Subscribers: bhushan, nitesh.jain, jaydeep, lldb-commits
Differential: http://reviews.llvm.org/D12275
llvm-svn: 245927
2015-08-25 09:52:59 +00:00
Pavel Labath 0f4b17d12c Simplify NativeThreadLinux includes
there is no need to include architecture-specific register contexts when the generic one will
suffice.

llvm-svn: 245839
2015-08-24 13:25:54 +00:00
Pavel Labath b9cc0c7593 [NativeProcessLinux] Pass around threads by reference
Summary:
Most NPL private functions took (shared) pointers to threads as arguments. This meant that the
callee could not be sure if the pointer was valid and so most functions were peppered with
null-checks. Now, I move the check closer to the source, and pass around the threads as
references (which are then assumed to be valid).

Reviewers: tberghammer

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D12237

llvm-svn: 245831
2015-08-24 09:22:04 +00:00
Pavel Labath f90777826a [NativeProcessLinux] Reduce the number of casts
Summary:
NPL used to be peppered with casts of the NativeThreadProtocol objects into NativeThreadLinux. I
move these closer to the source where we obtain these objects. This way, the rest of the code can
assume we are working with the correct type of objects.

Reviewers: ovyalov, tberghammer

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D12187

llvm-svn: 245681
2015-08-21 09:13:53 +00:00
Pavel Labath 0e1d729b75 [NativeProcessLinux] Fix a bug in instruction-stepping over thread creation
Summary:
There was a bug in NativeProcessLinux, where doing an instruction-level single-step over the
thread-creation syscall resulted in loss of control over the inferior. This happened because
after the inferior entered the thread-creation maintenance stop, we unconditionally performed a
PTRACE_CONT, even though the original intention was to do a PTRACE_SINGLESTEP. This is fixed by
storing the original state of the thread before the stop (stepping or running) and then
performing the appropriate action when resuming.

I also get rid of the callback in the ThreadContext structure, which stored the lambda used to
resume the thread, but which was not used consistently.

A test verifying the correctness of the new behavior is included.

Reviewers: ovyalov, tberghammer

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D12104

llvm-svn: 245545
2015-08-20 09:06:12 +00:00
Pavel Labath 78856474fb On Linux, clear the signal mask of the launched inferior
Summary:
Due to fork()/execve(), the launched inferior inherits the signal mask of its parent (lldb-server). But because lldb-server modifies its signal mask (It blocks SIGCHLD, for example), the inferior starts with some signals being initially blocked.

One consequence is that TestCallThatRestarts.ExprCommandThatRestartsTestCase (test/expression_command/call-restarts) fails because sigchld_handler() in lotta-signals.c is not called, due to the SIGCHLD signal being blocked.

To prevent the signal masking done by lldb-server from affecting the created inferior, the signal mask of the inferior is now cleared before the execve().

Patch by: Yacine Belkadi

Reviewers: ovyalov, labath

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D12138

llvm-svn: 245436
2015-08-19 13:47:57 +00:00
Omair Javaid dee4a867be Fix lldb-server arm-linux-g++ build
llvm-svn: 245428
2015-08-19 10:44:16 +00:00
Pavel Labath d2c4c9b132 [LLGS] Avoid misrepresenting log lines as inferior output
Summary:
in case we are logging to stdout, any log lines from the forked child can be misconstrued to be
inferior output. To avoid this, we disable all logging immediately after forking.

I also fix the implementatoion of DisableAllLogChannels, which was a no-op before this commit.

Reviewers: clayborg, ovyalov

Subscribers: dean, lldb-commits

Differential Revision: http://reviews.llvm.org/D12083

llvm-svn: 245272
2015-08-18 08:23:35 +00:00
Sagar Thakur 789da6678e [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support
This patch :

- Fixes offsets of all register sets for Mips.
- Adds MSA register set and FRE=1 mode support for FP register set.
- Separates lldb register numbers and register infos of freebsd/mips64 from linux/mips64.
- Re-orders the register numbers of all kinds for mips to be consistent with freebsd order of register numbers.

Reviewers: jaydeep, clayborg, jasonmolenda, ovyalov, emaste
Subscribers: tberghammer, ovyalov, emaste, mohit.bhakkad, nitesh.jain, bhushan
Differential: http://reviews.llvm.org/D10919
llvm-svn: 245217
2015-08-17 13:40:17 +00:00
Ravitheja Addepally 72ab9e5c6c Removing redundant check from r244875
llvm-svn: 244886
2015-08-13 11:53:23 +00:00
Tamas Berghammer 64ad85cef2 Fix Linux build after r244875
llvm-svn: 244877
2015-08-13 09:19:27 +00:00
Ravitheja Addepally 4778e410d0 Set orig_eax to -1 for Linux x86 platforms
Summary:
For Linux x86 based environments the orig_eax/orig_rax
register should be set to -1 to prevent the instruction pointer
to be decremented, which was the cause for the SIGILL exception.

Fix for Bug 23659

Reviewers: zturner, ashok.thirumurthi, mikesart, jingham, clayborg

Subscribers: clayborg, labath

Differential Revision: http://reviews.llvm.org/D11411

llvm-svn: 244875
2015-08-13 09:05:11 +00:00
Jaydeep Patil 831435042e [LLDB][MIPS] Handle false positives for MIPS hardware watchpoints
SUMMARY:
    Last 3bits of the watchpoint address are masked by the kernel. For example, n is 
    at 0x120010d00 and m is 0x120010d04. When a watchpoint is set at m, then watch 
    exception is generated even when n is read/written. To handle this case, instruction 
    at PC is emulated to find the base address of the load/store instruction. This address 
    is then appended to the description of the stop-info packet. Client then reads this 
    information to check whether the user has set a watchpoint on this address.
    
    Reviewers: jingham, clayborg
    Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
    Differential Revision: http://reviews.llvm.org/D11672

llvm-svn: 244864
2015-08-13 03:44:09 +00:00
Omair Javaid 1fd2a8cfa7 Fix AArch64 watchpoint handlers in NativeRegisterContextLinux_arm64
http://reviews.llvm.org/D11899

llvm-svn: 244750
2015-08-12 13:42:24 +00:00
Tamas Berghammer 40caea63c4 Fix read only watchpoints on x86_64
On x86/x86_64 read only watchpoints aren't supported. Fall back
to read/write watchpoints in that case.

Note: Logic should be added to ignore the watchpoint hit when
occurred because of a write.

llvm-svn: 244742
2015-08-12 12:22:42 +00:00
Omair Javaid cf8eb9da4d Fix LLGS to enable read type watchpoints
http://reviews.llvm.org/D11902

llvm-svn: 244741
2015-08-12 11:30:21 +00:00
Oleksiy Vyalov 9dcdd2ee03 Revert r244308 since it's introducing test regressions on Linux:
- TestLldbGdbServer.py both clang & gcc, i386 and x86_64
 - TestConstVariables.py gcc, i386 and x86_64
 - 112 failures clang, i386

llvm-svn: 244514
2015-08-10 21:49:50 +00:00
Omair Javaid 2040548fcb Fix for build errors on arm-linux-gnueabi-gcc
http://reviews.llvm.org/D11256

llvm-svn: 244419
2015-08-09 19:04:41 +00:00
Sagar Thakur d754890047 [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support
This change :

    - Fixes offsets of all register sets for Mips.
    - Adds MSA register set and FRE=1 mode support for FP register set.
    - Separates lldb register numbers and register infos of freebsd/mips64 from linux/mips64.
    - Re-orders the register numbers of all kinds for mips to be consistent with freebsd order of register numbers.
    - Eliminates ENABLE_128_BIT_SUPPORT and union ValueData from Scalar.cpp and uses llvm::APInt and llvm::APFloat for all integer and floating point types.

Reviewers : emaste, jaydeep, clayborg
Subscribers : emaste, mohit.bhakkad, nitesh.jain, bhushan
Differential : http://reviews.llvm.org/D10919

llvm-svn: 244308
2015-08-07 06:39:38 +00:00
Mohit K. Bhakkad 3681c5b850 [LLDB][MIPS] To handle SI_KERNEL generated for invalid 64 bit address
Patch by Nitesh Jain

Reviewers: clayborg, ovyalov.
Subscribers: jaydeep, bhushan, mohit.bhakkad, sagar, emaste, lldb-commits.
Differential Revision: http://reviews.llvm.org/D11176

llvm-svn: 243620
2015-07-30 05:38:11 +00:00
Pavel Labath 162fb8e8ab Speed up NativeProcessLinux::GetLoadedModuleFileSpec
Summary:
GetLoadedModuleFileSpec was reading /proc/pid/maps character by character, which was very slow,
since we do that for every shared library, which android tends to have a lot. Switching to
ProcFileReader saves us about 0.4 seconds in attach time.

Reviewers: tberghammer

Subscribers: tberghammer, danalbert, lldb-commits

Differential Revision: http://reviews.llvm.org/D11460

llvm-svn: 243019
2015-07-23 14:47:33 +00:00
Pavel Labath 79203995fa [NativeProcessLinux] Fix a couple of warnings
llvm-svn: 243013
2015-07-23 13:07:37 +00:00
Pavel Labath 05569f679a Add jstopinfo support to llgs
Summary:
This adds support for jstopinfo field of stop-reply packets. This field enables us to avoid
querying full thread stop data on most stops  (see r242593 for more details).

Reviewers: ovyalov, clayborg

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D11415

llvm-svn: 242997
2015-07-23 09:09:29 +00:00
Pavel Labath cb213b3831 Fix warnings found by -Wextra-semi
patch by Eugene Zelenko.

llvm-svn: 242875
2015-07-22 08:12:01 +00:00
Pavel Labath 19cbe96a45 [NativeProcessLinux] Integrate MainLoop
Summary:
This commit integrates MainLoop into NativeProcessLinux. By registering a SIGCHLD handler with
the llgs main loop, we can get rid of the special monitor thread in NPL, which saves as a lot of
thread ping-pong when responding to client requests (e.g. qThreadInfo processing time has been
reduced by about 40%). It also makes the code simpler, IMHO.

Reviewers: ovyalov, clayborg, tberghammer, chaoren

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D11150

This is a resubmission of r242305 after it was reverted due to bad interactions with the stdio
thread.

llvm-svn: 242783
2015-07-21 13:20:32 +00:00
Pavel Labath 44e82db291 [NativeProcessLinux] Bugfix in the monitor thread
Make sure we dont treat EINTR as a fatal error. I was getting this when trying to profile the
debugger. I'm not sure why this wasn't surfacing before, it could be that the profiler is using
some signals internally.

llvm-svn: 242681
2015-07-20 16:14:46 +00:00
Pavel Labath 5abe726911 Revert "[NativeProcessLinux] Integrate MainLoop"
This seems to be causing major slowdows on the android buildbot. Reverting while I investigate.

llvm-svn: 242391
2015-07-16 08:45:03 +00:00