a8fd7fdc25
Detabify
...
llvm-svn: 36891
2007-05-06 20:14:21 +00:00
4cb9eb81ef
A bitcast of a global variable may have been constant folded to a GEP -
...
handle this case too.
llvm-svn: 36745
2007-05-04 17:12:26 +00:00
8c78a0bff0
Drop 'const'
...
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
11940fbba3
Properly set arguments bitwidth of EHSELECT node
...
llvm-svn: 36654
2007-05-02 22:15:48 +00:00
e95c6ad802
Use 'static const char' instead of 'static const int'.
...
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
2007-05-02 21:39:20 +00:00
09f162ca6a
Do not use typeinfo to identify pass in pass manager.
...
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
8cfd33b647
Continue refactoring inline asm code. If there is an earlyclobber output
...
register, preallocate all input registers and the early clobbered output.
This fixes PR1357 and CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
llvm-svn: 36599
2007-04-30 21:11:17 +00:00
4333f8b1cf
refactor GetRegistersForValue to take OpInfo as an argument instead of various
...
pieces of it. No functionality change.
llvm-svn: 36592
2007-04-30 17:29:31 +00:00
ef07332504
refactor some code, no functionality change
...
llvm-svn: 36590
2007-04-30 17:16:27 +00:00
412d61af43
generalize aggregate handling
...
llvm-svn: 36568
2007-04-29 18:58:03 +00:00
401d8db381
memory operands that have a direct operand should have their stores created
...
before the copies into physregs are done. This avoids having flag operands
skip the store, causing cycles in the dag at sched time. This fixes infinite
loops on these tests:
test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308
test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828
llvm-svn: 36547
2007-04-28 21:12:06 +00:00
de339fa55d
eliminate more redundant constraint type analysis
...
llvm-svn: 36546
2007-04-28 21:03:16 +00:00
b2e55562ed
merge constraint type analysis stuff together.
...
llvm-svn: 36545
2007-04-28 21:01:43 +00:00
d7e3b6c442
Significant refactoring of the inline asm stuff, to support future changes.
...
No functionality change.
llvm-svn: 36544
2007-04-28 20:49:53 +00:00
1deacd61f4
memory inputs to an inline asm are required to have an address available.
...
If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.
This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
llvm-svn: 36536
2007-04-28 06:42:38 +00:00
d102ed0ac6
Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll and
...
CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
llvm-svn: 36534
2007-04-28 06:08:13 +00:00
4df3e8093b
Fix this to match change to InlineAsm class.
...
llvm-svn: 36524
2007-04-28 04:05:59 +00:00
784fe9dbbb
improve EH global handling, patch by Duncan Sands.
...
llvm-svn: 36499
2007-04-27 01:20:11 +00:00
8131ab7c0f
enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrap
...
successfully! woohoo...
llvm-svn: 36496
2007-04-26 21:09:43 +00:00
d7ae7f1659
Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32
...
llvm-svn: 36490
2007-04-26 20:44:04 +00:00
15f269afa3
This was lefted out. Fixed sumarray-dbl.
...
llvm-svn: 36445
2007-04-25 18:33:21 +00:00
cb0ed0cfbd
allow support for 64-bit stack objects
...
llvm-svn: 36420
2007-04-25 04:08:28 +00:00
47917b697f
Assertion when using a 1-element vector for an add operation. Get the
...
real vector type in this case.
llvm-svn: 36402
2007-04-24 21:13:23 +00:00
4cfa616cee
Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about
...
tests always being true in the process.
llvm-svn: 36387
2007-04-24 01:24:20 +00:00
8af6d5896f
PR400 phase 2. Propagate attributed load/store information through DAGs.
...
llvm-svn: 36356
2007-04-22 23:15:30 +00:00
0c1349e6bc
Revert Christopher Lamb's load/store alignment changes.
...
llvm-svn: 36309
2007-04-21 18:36:27 +00:00
bff50208c8
add support for alignment attributes on load/store instructions
...
llvm-svn: 36301
2007-04-21 08:16:25 +00:00
6bd7b7b30b
disable switch lowering using shift/and. It still breaks ppc bootstrap for
...
some reason. :( Will investigate.
llvm-svn: 36011
2007-04-14 19:39:41 +00:00
8a1a84f96e
Fix PR1325: Case range optimization was performed in the case it
...
shouldn't. Also fix some "latent" bug on 64-bit platforms
llvm-svn: 35990
2007-04-14 13:25:55 +00:00
7196f09edc
disable shift/and lowering to work around PR1325 for now.
...
llvm-svn: 35985
2007-04-14 02:26:56 +00:00
e288040abf
Fix PR1323 : we haven't updated phi nodes in good manner :)
...
llvm-svn: 35963
2007-04-13 06:53:51 +00:00
5111499136
the result of an inline asm copy can be an arbitrary VT that the register
...
class supports. In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector
result to the right type. This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
llvm-svn: 35944
2007-04-12 06:00:20 +00:00
c6251a7dfd
For PR1284:
...
Implement the "part_set" intrinsic.
llvm-svn: 35938
2007-04-12 02:48:46 +00:00
a472f66dd0
For PR1146:
...
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.
llvm-svn: 35877
2007-04-11 02:44:20 +00:00
f269d84ca0
apparently some people commit without building the tree, or they forget to
...
commit a LOT of files.
llvm-svn: 35858
2007-04-10 03:20:39 +00:00
e0bbbd3774
No longer needed.
...
llvm-svn: 35850
2007-04-09 23:42:32 +00:00
da964a2852
Use integer log for metric calculation
...
llvm-svn: 35834
2007-04-09 21:57:03 +00:00
0475f3b4e9
Unbreak VC++ build.
...
llvm-svn: 35817
2007-04-09 14:32:59 +00:00
506eaf7915
Next stage into switch lowering refactoring
...
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.
llvm-svn: 35816
2007-04-09 12:31:58 +00:00
71b79e3d99
For PR1146:
...
Adapt handling of parameter attributes to use the new ParamAttrsList class.
llvm-svn: 35814
2007-04-09 06:17:21 +00:00
7b2decfa0a
implement CodeGen/X86/inline-asm-x-scalar.ll:test3
...
llvm-svn: 35802
2007-04-09 05:31:20 +00:00
b49917da92
Fix PR1316
...
llvm-svn: 35783
2007-04-09 00:33:58 +00:00
e55ecfb870
Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314
...
llvm-svn: 35779
2007-04-08 22:23:26 +00:00
1c741e95d3
minor comment fix
...
llvm-svn: 35696
2007-04-06 17:47:14 +00:00
85460acfbf
Change the bit_part_select (non)implementation from "return 0" to abort.
...
llvm-svn: 35679
2007-04-05 01:20:18 +00:00
cce90f55ed
Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
...
llvm-svn: 35678
2007-04-04 23:48:25 +00:00
915e61736b
Properly emit range comparisons for switch cases, where neighbour cases
...
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase
llvm-svn: 35672
2007-04-04 21:14:49 +00:00
3a0843e734
For PR1297:
...
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.
llvm-svn: 35546
2007-04-01 07:34:11 +00:00
f6a6d3c8b0
move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare".
...
llvm-svn: 35529
2007-03-31 04:18:03 +00:00
4388043b25
Scale 1 is always ok.
...
llvm-svn: 35407
2007-03-28 01:55:52 +00:00
07c42d43a2
GEP index sinking fixes:
...
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).
llvm-svn: 35403
2007-03-28 01:49:39 +00:00
37a0bfe128
Remove dead code
...
llvm-svn: 35380
2007-03-27 12:05:48 +00:00
3a9d68181a
Split big monster into small helpers. No functionality change.
...
llvm-svn: 35379
2007-03-27 11:29:11 +00:00
c42406b5ad
SDISel does not preserve all, it changes CFG and other info.
...
llvm-svn: 35376
2007-03-27 00:53:36 +00:00
7037826c86
First step of switch lowering refactoring: perform worklist-driven
...
strategy, emit JT's where possible.
llvm-svn: 35338
2007-03-25 15:07:15 +00:00
77f0479833
Implement support for vector operands to inline asm, implementing
...
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
llvm-svn: 35332
2007-03-25 05:00:54 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
dcb291faa4
Change uses of Function::front to Function::getEntryBlock for readability.
...
llvm-svn: 35265
2007-03-22 16:38:57 +00:00
550cf0369c
Minor bug.
...
llvm-svn: 35219
2007-03-20 19:32:11 +00:00
a2465dfc07
Use SmallSet instead of std::set.
...
llvm-svn: 35133
2007-03-17 08:53:30 +00:00
be22235790
If sdisel has decided to sink GEP index expression into any BB. Replace all uses
...
in that BB.
llvm-svn: 35132
2007-03-17 08:22:49 +00:00
c5bc763f50
Turn on GEP index sinking by default.
...
llvm-svn: 35127
2007-03-16 18:32:30 +00:00
0a9d0cabaf
Stupid bug.
...
llvm-svn: 35126
2007-03-16 17:50:20 +00:00
009ea54262
Sink a binary expression into its use blocks if it is a loop invariant
...
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.
llvm-svn: 35123
2007-03-16 08:46:27 +00:00
ce8aba03ee
implement support for floating point constants used as inline asm memory operands.
...
llvm-svn: 35033
2007-03-08 22:29:47 +00:00
b7bc3f2d30
make this fail even in non-assert builds.
...
llvm-svn: 35025
2007-03-08 07:07:03 +00:00
ed4b303c10
Refactoring of formal parameter flags. Enable properly use of
...
zext/sext/aext stuff.
llvm-svn: 35008
2007-03-07 16:25:09 +00:00
f0b9316552
Enumerate SDISel formal parameter attributes. Make use of new
...
enumeration.
llvm-svn: 34960
2007-03-06 06:10:33 +00:00
b622c11f77
Unbreak VC++ build.
...
llvm-svn: 34917
2007-03-05 00:00:42 +00:00
d5453d7b56
Lower eh filter intrinsic.
...
llvm-svn: 34802
2007-03-01 20:24:30 +00:00
cf465fcebc
MERGE_VALUES unnecessary.
...
llvm-svn: 34750
2007-02-28 18:37:04 +00:00
ab5d0ac02c
track signedness of formal argument, though we have a fixme here.
...
llvm-svn: 34620
2007-02-26 02:56:58 +00:00
14059d958a
Fix for PR1224.
...
llvm-svn: 34610
2007-02-25 21:43:59 +00:00
8c504cf9a0
optimize duplicate ValueMap lookups
...
llvm-svn: 34599
2007-02-25 18:40:32 +00:00
e1d1c0590f
Deal with cases when MMI is not requested.
...
llvm-svn: 34556
2007-02-24 09:45:44 +00:00
31fef788eb
Handle improper cast.
...
llvm-svn: 34535
2007-02-23 21:45:01 +00:00
44c37e7dbf
Tighten up error checking of args.
...
llvm-svn: 34493
2007-02-22 16:10:05 +00:00
504e99479c
Handle lowering invoke to call correctly.
...
llvm-svn: 34492
2007-02-22 15:38:06 +00:00
4b37a4c712
Selection and lowering for exception handling.
...
llvm-svn: 34481
2007-02-21 22:53:45 +00:00
09575bac2e
For PR1195:
...
Change use of "packed" term to "vector" in comments, strings, variable
names, etc.
llvm-svn: 34300
2007-02-15 03:39:18 +00:00
d84d35ba70
For PR1195:
...
Rename PackedType -> VectorType, ConstantPacked -> ConstantVector, and
PackedTyID -> VectorTyID. No functional changes.
llvm-svn: 34293
2007-02-15 02:26:10 +00:00
ab1812f806
fix a warning
...
llvm-svn: 34272
2007-02-14 07:34:56 +00:00
1cf84d2745
Refix CodeGen/Generic/switch-lower.ll. In contrast to my previous patch,
...
this doesn't miscompile lots of programs :)
llvm-svn: 34268
2007-02-14 07:18:16 +00:00
945e437c65
Generalize TargetData strings, to support more interesting forms of data.
...
Patch by Scott Michel.
llvm-svn: 34266
2007-02-14 05:52:17 +00:00
2fbff4d2dc
revert my previous switch lowering change, which miscompiles a few programs.
...
This will break a dj test until I have time to investigate.
llvm-svn: 34247
2007-02-13 20:09:07 +00:00
abde3cc16c
Add a space between // and the comment.
...
llvm-svn: 34244
2007-02-13 18:10:13 +00:00
9956dcffbe
Add "original alignment" to function arguments flags.
...
llvm-svn: 34240
2007-02-13 13:50:08 +00:00
9056bae3be
Fix switch lowering to order cases in zext order, which is how we emit the
...
comparisons. This fixes an infinite loop on CodeGen/Generic/switch-lower.ll
and PR1197
llvm-svn: 34216
2007-02-13 01:05:56 +00:00
c473d8e431
Privatize StructLayout::MemberOffsets, adding an accessor
...
llvm-svn: 34156
2007-02-10 19:55:17 +00:00
276b44b0f9
Add function live-ins to entry block live-in set.
...
llvm-svn: 34112
2007-02-10 02:43:39 +00:00
de6083463d
Rename some variables to avoid confusion with SelectionDAGISel::BB.
...
llvm-svn: 34110
2007-02-10 01:08:18 +00:00
289aa4495c
Switch VAlueMap from std::map to DenseMap.
...
llvm-svn: 33863
2007-02-04 01:35:11 +00:00
79084305ee
Switch NodeMap from std::map to DenseMap, this speeds up isel by 2.3%
...
llvm-svn: 33862
2007-02-04 01:31:47 +00:00
2341c22ec7
Changes to support making the shift instructions be true BinaryOperators.
...
This feature is needed in order to support shifts of more than 255 bits
on large integer types. This changes the syntax for llvm assembly to
make shl, ashr and lshr instructions look like a binary operator:
shl i32 %X, 1
instead of
shl i32 %X, i8 1
Additionally, this should help a few passes perform additional optimizations.
llvm-svn: 33776
2007-02-02 02:16:23 +00:00
296a83cefb
Fit in 80 columns
...
llvm-svn: 33745
2007-02-01 04:55:59 +00:00
e3eeb24a86
Emit a better assertion message for PR1133
...
llvm-svn: 33736
2007-02-01 01:21:12 +00:00
5301e7c605
For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid
...
confusion with external linkage types.
llvm-svn: 33663
2007-01-30 20:08:39 +00:00
d27f95e08d
add initial support for handling inline asms with multiple constraints.
...
This doesn't do the "right thing" but will probably work in most cases.
This implements CodeGen/PowerPC/2007-01-29-lbrx-asm.ll.
llvm-svn: 33643
2007-01-29 23:45:14 +00:00
eda5997cc8
Finish off bug 680, allowing targets to custom lower frame and return
...
address nodes.
llvm-svn: 33636
2007-01-29 22:58:52 +00:00
06f7d4bec7
Arguments are counting from 1. not from 0. Maybe we should change
...
numbering somehow? E.g. make return argument the last?
llvm-svn: 33606
2007-01-28 18:01:49 +00:00
9fa3839d29
More cleanup
...
llvm-svn: 33605
2007-01-28 16:04:40 +00:00
037c867b54
Propagate changes from my local tree. This patch includes:
...
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
llvm-svn: 33597
2007-01-28 13:31:35 +00:00
c56315c2b5
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
...
for debugging and exception handling.
llvm-svn: 33550
2007-01-26 21:22:28 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
...
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
2eadb5310d
For PR970:
...
Clean up handling of isFloatingPoint() and dealing with PackedType.
Patch by Gordon Henriksen!
llvm-svn: 33415
2007-01-21 00:29:26 +00:00
50ee0e40e5
Teach TargetData to handle 'preferred' alignment for each target, and use
...
these alignment amounts to align scalars when we can. Patch by Scott Michel!
llvm-svn: 33409
2007-01-20 22:35:55 +00:00
75b871fb1e
For PR1043:
...
Merge ConstantIntegral and ConstantBool into ConstantInt.
Remove ConstantIntegral and ConstantBool from LLVM.
llvm-svn: 33073
2007-01-11 12:24:14 +00:00
10cae15d8e
remove support for llvm.isunordered
...
llvm-svn: 32992
2007-01-07 08:37:22 +00:00
8ec5283dc4
GEP subscript is interpreted as a signed value.
...
llvm-svn: 32888
2007-01-05 01:46:20 +00:00
96035bed51
fix PowerPC/2007-01-04-ArgExtension.ll, a bug handling K&R prototypes with
...
the recent signless changes.
llvm-svn: 32884
2007-01-04 22:22:37 +00:00
e6f81876eb
Legalizer doesn't do an ANY_EXTEND if we don't ask for one so make sure
...
that we default to an ANY_EXTEND if no parameter attribute is set on the
result value of a function.
llvm-svn: 32836
2007-01-03 16:49:33 +00:00
2a34b91666
Restore previous behavior of defaulting to ZEXT. This works around two
...
things: (1) preventing PR1071 and (2) working around missing parameter
attributes for bool type. (2) will be fixed shortly. When PR1071 is fixed,
this patch should be undone.
llvm-svn: 32831
2007-01-03 05:03:05 +00:00
0917adf614
Two changes:
...
1. Switch expression and cases are compared signed and are sign extended.
2. For function results needing extended, do SIGN_EXTEND if the SExtAttribute
is set and ZERO_EXTEND if the ZExtAttribute is set, otherwise just let
the Legalizer do ANY_EXTEND.
This fixes the recent regression in kimwitu++ and probably the llvm-gcc
bootstrap issue we had today.
llvm-svn: 32830
2007-01-03 04:25:33 +00:00
e63b6518fa
For PR950:
...
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
llvm-svn: 32788
2006-12-31 05:55:36 +00:00
266e42b312
For PR950:
...
This patch removes the SetCC instructions and replaces them with the ICmp
and FCmp instructions. The SetCondInst instruction has been removed and
been replaced with ICmpInst and FCmpInst.
llvm-svn: 32751
2006-12-23 06:05:41 +00:00
258657e64e
getLoad() and getStore() calls missed SVOffset operand. Thanks to Dan Gohman
...
for pointing it out!
llvm-svn: 32712
2006-12-20 01:27:29 +00:00
9bd5ed636c
Fix PR1049 and CodeGen/Generic/2006-12-16-InlineAsmCrash.ll
...
by producing target constants instead of constants. Constants can get
selected to li/movri instructions, which causes the scheduler to explode.
llvm-svn: 32633
2006-12-16 21:14:48 +00:00
22cf89967b
More soft-fp work.
...
llvm-svn: 32559
2006-12-13 20:57:08 +00:00
bfe26ffcfc
Replace CastInst::createInferredCast calls with more accurate cast
...
creation calls.
llvm-svn: 32521
2006-12-13 00:50:17 +00:00
634885f71e
Expand i32/i64 CopyToReg f32/f64 to BIT_CONVERT + CopyToReg.
...
llvm-svn: 32493
2006-12-12 21:21:32 +00:00
0c0b78c18e
Expand formal arguments and call arguments recursively: e.g. f64 -> i64 -> 2 x i32.
...
llvm-svn: 32476
2006-12-12 07:27:38 +00:00
3b7c257cae
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
...
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
llvm-svn: 32415
2006-12-10 23:12:42 +00:00
4eee72471c
Preliminary soft float support.
...
llvm-svn: 32394
2006-12-09 02:42:38 +00:00
22e978a736
Removing even more <iostream> includes.
...
llvm-svn: 32320
2006-12-07 20:04:42 +00:00
feba507a97
Fix for PR1023 by Dan Gohman.
...
llvm-svn: 32003
2006-11-29 01:58:12 +00:00
6e12a052ff
Fix for PR1022 (folding loads of static initializers) by Dan Gohman.
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llvm-svn: 32000
2006-11-29 01:38:07 +00:00
90f4238c38
add a hook to allow targets to hack on inline asms to lower them to llvm
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when they want to.
llvm-svn: 31997
2006-11-29 01:12:32 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
6c38f0bb07
For PR950:
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The long awaited CAST patch. This introduces 12 new instructions into LLVM
to replace the cast instruction. Corresponding changes throughout LLVM are
provided. This passes llvm-test, llvm/test, and SPEC CPUINT2000 with the
exception of 175.vpr which fails only on a slight floating point output
difference.
llvm-svn: 31931
2006-11-27 01:05:10 +00:00
d9436b6837
For PR950:
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First in a series of patches to convert SetCondInst into ICmpInst and
FCmpInst using only two opcodes and having the instructions contain their
predicate value. Nothing uses these classes yet. More patches to follow.
llvm-svn: 31867
2006-11-20 01:22:35 +00:00
30d08801ef
remove dead #include
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llvm-svn: 31753
2006-11-15 17:51:15 +00:00
d5e604dbb2
commentate
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llvm-svn: 31627
2006-11-10 04:41:34 +00:00
fdff938a7e
For PR950:
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This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.
llvm-svn: 31542
2006-11-08 06:47:33 +00:00
de46e48420
For PR786:
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Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
llvm-svn: 31380
2006-11-02 20:25:50 +00:00
7eb55b395f
For PR950:
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Replace the REM instruction with UREM, SREM and FREM.
llvm-svn: 31369
2006-11-02 01:53:59 +00:00
55402d4403
Allow the getRegForInlineAsmConstraint method to return a register class with
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no fixes physreg. Treat this as permission to use any register in the register
class. When this happens and it is safe, allow the llvm register allcoator to
allocate the register instead of doing it at isel time. This eliminates a ton
of copies around common inline asms. For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
llvm-svn: 31366
2006-11-02 01:41:49 +00:00
fe43befeda
Compile CodeGen/PowerPC/fp-branch.ll to:
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_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
instead of:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
llvm-svn: 31330
2006-10-31 23:06:00 +00:00
427301fdae
look through isunordered to inline it into branch blocks.
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llvm-svn: 31328
2006-10-31 22:37:42 +00:00
6f043b90ea
TargetLowering::isOperandValidForConstraint
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llvm-svn: 31319
2006-10-31 19:41:18 +00:00
968f803928
Turn an assert into an error message. This is commonly triggered when
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we don't support a specific constraint yet. When this happens, print the
unsupported constraint.
llvm-svn: 31310
2006-10-31 07:33:13 +00:00
84a28d4e76
Lower jumptable to BR_JT. The legalizer can lower it to a BRIND or let the target custom lower it.
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llvm-svn: 31293
2006-10-30 08:00:44 +00:00
e60ae823e8
fix Generic/2006-10-29-Crash.ll
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llvm-svn: 31281
2006-10-29 21:01:20 +00:00
f31b9ef458
Fix a load folding issue that Evan noticed: there is no need to export values
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used by comparisons in the main block.
llvm-svn: 31279
2006-10-29 18:23:37 +00:00
bba52191fa
split critical edges more carefully and intelligently. In particular, critical
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edges whose destinations are not phi nodes don't bother us. Also, share
split edges, since the split edge can't have a phi. This significantly
reduces the complexity of generated code in some cases.
llvm-svn: 31274
2006-10-28 19:22:10 +00:00
3e6b1c6157
Split *all* critical edges before isel. This resolves issues with spill code
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being inserted on unsplit critical edges, which introduces (sometimes large
amounts of) partially dead spill code.
This also fixes PR925 + CodeGen/Generic/switch-crit-edge-constant.ll
llvm-svn: 31260
2006-10-28 17:04:37 +00:00
84a035056e
Fix a bug in merged condition handling (CodeGen/Generic/2006-10-27-CondFolding.ll).
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Add many fewer CFG edges and PHI node entries. If there is a switch which has
the same block as multiple destinations, only add that block once as a successor/phi
node (in the jumptable case)
llvm-svn: 31242
2006-10-27 23:50:33 +00:00
b9392fb635
remove debug code
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llvm-svn: 31233
2006-10-27 21:58:03 +00:00
f1b54fd7a5
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
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cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
llvm-svn: 31232
2006-10-27 21:54:23 +00:00
ed0110b949
Turn conditions like x<Y|z==q into multiple blocks.
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This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-27 21:36:01 +00:00
7e80b0b31e
For PR950:
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Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.
llvm-svn: 31195
2006-10-26 06:15:43 +00:00
Anton Korobeynikov