3 Commits

Author	SHA1	Message	Date
Daniel Sanders	1779314e3c	[mips] Add backend support for Mips32r[35] and Mips64r[35]. ... Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695	2015-02-18 16:24:50 +00:00
Vasileios Kalintiris	ef96a8ecd6	[mips] Enable arithmetic and binary operations for the i128 data type. ... Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089	2015-01-26 12:33:22 +00:00
Vasileios Kalintiris	b2dd15f8c7	[mips] Add preliminary support for the MIPS II target. ... Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686	2014-11-11 11:43:55 +00:00