129819de71
move a few more symbols to .rodata
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llvm-svn: 92011
2009-12-23 17:48:10 +00:00
a864a67185
Use more sensible type for flags in asms. PR 5570.
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Patch by Sylve`re Teissier (sorry, ASCII only).
llvm-svn: 91988
2009-12-23 07:32:51 +00:00
fdb33458fc
Update objectsize intrinsic and associated dependencies. Fix
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lowering code and update testcases.
llvm-svn: 91979
2009-12-23 02:51:48 +00:00
0602f39bb1
Remove superfluous SDNode ordering.
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llvm-svn: 91971
2009-12-23 01:28:19 +00:00
9df5c6dfc3
Remove node ordering from inline asm nodes. It's not needed.
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llvm-svn: 91961
2009-12-23 00:47:20 +00:00
91313064f1
Remove node ordering from VA nodes. It's not needed.
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llvm-svn: 91958
2009-12-23 00:44:51 +00:00
ef408db250
Revert r91949 r91942 and r91936.
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llvm-svn: 91953
2009-12-23 00:28:23 +00:00
54dd5398e0
Finish up node ordering in ExpandNode.
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llvm-svn: 91949
2009-12-23 00:05:09 +00:00
ad1fdf0e40
Assign ordering to nodes created in ExpandNode. Only roughly 1/2 of the function
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is finished.
llvm-svn: 91942
2009-12-22 23:44:56 +00:00
70794596a8
Assign ordering to SDNodes in PromoteNode. Also fixing a subtle bug where BSWAP
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was using "Tmp1" in the first getNode call instead of Node->getOperand(0).
llvm-svn: 91936
2009-12-22 22:53:39 +00:00
d85498132f
Allow 0 as an order number. Don't assign an order to formal arguments.
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llvm-svn: 91920
2009-12-22 21:35:02 +00:00
bac37abe73
Report an error for bad inline assembly, where the value passed for an
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"indirect" operand is not a pointer.
llvm-svn: 91913
2009-12-22 18:34:19 +00:00
919b7aab2e
Add more plumbing. This time in the LowerArguments and "get" functions which
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return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
llvm-svn: 91880
2009-12-22 02:10:19 +00:00
ac08758b71
Add SDNode ordering to inlined asm and VA functions.
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llvm-svn: 91876
2009-12-22 01:25:10 +00:00
f376c40d0e
Adding more assignment of ordering to SDNodes. This time in the "call" and
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generic copy functions.
llvm-svn: 91872
2009-12-22 01:11:43 +00:00
a4d7df7a37
Add ordering of SDNodes to LowerCallTo.
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llvm-svn: 91866
2009-12-22 00:50:32 +00:00
b99b2693f3
Now add ordering to SDNodes created by the massive intrinsic lowering function.
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llvm-svn: 91863
2009-12-22 00:40:51 +00:00
ea3e73e596
To make things interesting, I added MORE code to set the ordering of
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SDNodes. This time in the load/store and limited-precision code.
llvm-svn: 91860
2009-12-22 00:12:37 +00:00
c6b473433b
Add more plumbing to assign ordering to SDNodes. Have the "getValue" method
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assign the ordering when called. Combine some of the ordering assignments to
keep things simple.
llvm-svn: 91857
2009-12-21 23:47:40 +00:00
e79105b591
More ordering plumbing. This time for GEP. I need to remember to assign
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orderings to values returned by getValue().
llvm-svn: 91850
2009-12-21 23:10:19 +00:00
fff99f066b
Another incremental check-in for assigning ordering to SDNodes. This time for
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shuffle and insert vector.
llvm-svn: 91847
2009-12-21 22:42:14 +00:00
443d0722b0
Assign ordering to more instructions. Incremental check-in.
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llvm-svn: 91846
2009-12-21 22:30:11 +00:00
28727f3785
- Add a bit more plumbing assigning an order to SDNodes.
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- Modify the "dump" method to emit the order of an SDNode.
llvm-svn: 91845
2009-12-21 21:59:52 +00:00
7f5eb53ce2
First wave of plumbing for assigning an ordering to SDNodes. This takes care of
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a lot of the branching instructions.
llvm-svn: 91838
2009-12-21 19:59:38 +00:00
6de55a0efd
Place SDNodeOrdering.h in the directory it's used.
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llvm-svn: 91834
2009-12-21 19:34:59 +00:00
10590171fa
Use 4-arg getVTList) variant instead of generic one, when possible
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llvm-svn: 91744
2009-12-19 02:04:00 +00:00
022d18fa3f
Changes from review:
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- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
doesn't conflate construction with storage.
- Move assigning the ordering into the SelectionDAGBuilder.
This isn't used yet, so there should be no functional changes.
llvm-svn: 91727
2009-12-18 23:32:53 +00:00
b175de6356
Increase opportunities to optimize (brcond (srl (and c1), c2)).
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llvm-svn: 91717
2009-12-18 21:31:31 +00:00
3152b0471b
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
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The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
llvm-svn: 91649
2009-12-18 01:03:29 +00:00
df5561db78
Introduce EVT::getHalfSizedIntegerVT() for use in ExpandUnalignedStore() in
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LegalizeDAG.cpp. Unlike the code it replaces, which simply decrements the simple
type by one, getHalfSizedIntegerVT() searches for the smallest simple integer
type that is at least half the size of the type it is called on. This approach
has the advantage that it will continue working if a new value type (such as
i24) is added to MVT.
Also, in preparation for new value types, remove the assertions that
non-power-of-2 8-bit-mutiple types are Extended when legalizing extload and
truncstore operations.
llvm-svn: 91614
2009-12-17 20:09:43 +00:00
1c00b6964f
Fix a comment grammaro.
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llvm-svn: 91584
2009-12-17 05:07:36 +00:00
aadf060b92
Revert this dag combine change:
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Fold (zext (and x, cst)) -> (and (zext x), cst)
DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping.
llvm-svn: 91574
2009-12-17 00:40:05 +00:00
b827e52638
Reapply r91392, it was only unmasking the bug, and since TOT is still broken having it reverted does no good.
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llvm-svn: 91560
2009-12-16 20:10:05 +00:00
df45b70c1e
Revert "Initial work on disabling the scheduler. This is a work in progress, and
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this", this broke llvm-gcc bootstrap for release builds on
x86_64-apple-darwin10.
llvm-svn: 91533
2009-12-16 10:56:02 +00:00
852c486946
Make 91378 more conservative.
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1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.
llvm-svn: 91399
2009-12-15 03:00:32 +00:00
07beddceb7
Initial work on disabling the scheduler. This is a work in progress, and this
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stuff isn't used just yet.
We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2'
flags. The hypothesis is that the people who use these flags know what they are
doing, and have hand-optimized the C code to reduce latencies and other
conflicts.
The idea behind our scheme to turn off scheduling is to create a map "on the
side" during DAG generation. It will order the nodes by how they appeared in the
code. This map is then used during scheduling to get the ordering.
llvm-svn: 91392
2009-12-15 01:54:51 +00:00
d1521ef40c
Fold (zext (and x, cst)) -> (and (zext x), cst).
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llvm-svn: 91380
2009-12-15 00:52:11 +00:00
ca7c690d3b
Propagate zest through logical shift.
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llvm-svn: 91378
2009-12-15 00:41:36 +00:00
cecad35728
Fix integer cast code to handle vector types.
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llvm-svn: 91362
2009-12-14 23:40:38 +00:00
6453a4e2ab
Fix this to properly clear the FastISel debug location. Thanks to
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Bill for spotting this!
llvm-svn: 91355
2009-12-14 23:08:09 +00:00
94b6310136
Fix weird typo which leads to unallocated memory access for nodes with 4 results.
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llvm-svn: 91233
2009-12-13 01:00:59 +00:00
619a78bd59
Delete an unnecessary line. The VTSDNode on a SIGN_EXTEND_REG is never
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a vector type.
llvm-svn: 91181
2009-12-11 23:26:08 +00:00
1d459e4937
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.
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llvm-svn: 91158
2009-12-11 21:31:27 +00:00
6d306bb32b
Fix the result type of SELECT nodes lowered from Select instructions with
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aggregate return values. This fixes PR5754.
llvm-svn: 91145
2009-12-11 19:50:50 +00:00
d938faff4b
Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.
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llvm-svn: 90925
2009-12-09 01:53:58 +00:00
f5938d5d27
Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes.
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llvm-svn: 90922
2009-12-09 01:36:00 +00:00
2d412f0cb8
Infer alignment for non-fixed stack object.
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llvm-svn: 90919
2009-12-09 01:17:24 +00:00
1750009f38
Add const qualifier.
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llvm-svn: 90918
2009-12-09 01:10:37 +00:00
34a23ea371
Refactor InferAlignment out of DAGCombine.
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llvm-svn: 90917
2009-12-09 01:04:59 +00:00
1bcece70bd
Truncate the arguments of llvm.frameaddress / llvm.returnaddress intrinsics from i32 to platform's largest native type
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llvm-svn: 90741
2009-12-07 02:28:26 +00:00
Nuno Lopes