398932a619
Move kill flags when the same register occurs more than once in a sequence.
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llvm-svn: 92058
2009-12-23 21:34:03 +00:00
0fa4fe0b9b
Handle undef operands properly.
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llvm-svn: 92054
2009-12-23 21:28:42 +00:00
8921d4cd98
Make insert position available to MergeOpsUpdate.
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Rearrange arguments.
No functional changes
llvm-svn: 92053
2009-12-23 21:28:37 +00:00
64870c5d93
Perform kill flag calculations in new method. No functional changes.
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llvm-svn: 92052
2009-12-23 21:28:31 +00:00
655e4e6028
Move repeated code to a new method. No functional change.
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llvm-svn: 92051
2009-12-23 21:28:23 +00:00
b05fbe1486
Add a SPR register class to the ARM target.
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Certain Thumb instructions require only SP (e.g. tSTRspi).
llvm-svn: 91944
2009-12-22 23:54:44 +00:00
6f579c12b1
Use proper move instructions. Make the verifier happy.
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llvm-svn: 91914
2009-12-22 18:49:55 +00:00
919b7aab2e
Add more plumbing. This time in the LowerArguments and "get" functions which
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return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
llvm-svn: 91880
2009-12-22 02:10:19 +00:00
db4d798619
Delete the instruction just before the function terminates for consistency sake.
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llvm-svn: 91836
2009-12-21 19:53:39 +00:00
740ab38bb7
Fix a bunch of little errors that Clang complains about when its being pedantic
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llvm-svn: 91764
2009-12-19 07:05:23 +00:00
b73b4fd30e
Fix libstdc++ build on ARM linux and part of PR5770.
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MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done.
Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts.
For a patch that make us detect problems like this earlier, take a look at
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html
With that patch we assert as soon and the new instruction is added to the garbage set.
llvm-svn: 91691
2009-12-18 16:59:39 +00:00
3152b0471b
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
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The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
llvm-svn: 91649
2009-12-18 01:03:29 +00:00
7f30b64dce
Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
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llvm-svn: 91571
2009-12-16 23:36:52 +00:00
30f2ac714b
Silence a clang warning about the deprecated (but perfectly reasonable in
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context) increment-of-bool idiom.
llvm-svn: 91564
2009-12-16 20:31:50 +00:00
69461f50c1
Mark STREX* as earlyclobber for the success result register.
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llvm-svn: 91555
2009-12-16 19:44:06 +00:00
466231ab92
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
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bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
llvm-svn: 91496
2009-12-16 02:32:54 +00:00
826ca5630e
Every anonymous namespace is different. Caught by clang++.
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llvm-svn: 91481
2009-12-16 00:15:28 +00:00
e0d8e14e11
Change indirect-globals to use a dedicated allocIndirectGV. This lets us
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remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface. It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.
llvm-svn: 91464
2009-12-15 22:42:46 +00:00
c28e629c2d
Added encoding bits for the Thumb ISA. Initial checkin.
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llvm-svn: 91434
2009-12-15 17:24:14 +00:00
ea8f6e31a0
nand atomic requires opposite operand ordering
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llvm-svn: 91371
2009-12-15 00:12:35 +00:00
bee6f16fed
Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate
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between BR_JTr and STREXD.
llvm-svn: 91339
2009-12-14 21:51:34 +00:00
3974a80307
v6 sync insn copy/paste error
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llvm-svn: 91333
2009-12-14 21:33:32 +00:00
3c4f04112a
Add ARMv6 memory and sync barrier instructions
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llvm-svn: 91329
2009-12-14 21:24:16 +00:00
acba3b0ae2
Fixed encoding bits typo of ldrexd/strexd.
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llvm-svn: 91327
2009-12-14 21:01:46 +00:00
57ccc19617
Thumb2 atomic operations
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llvm-svn: 91321
2009-12-14 20:14:59 +00:00
fed3d088ce
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
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llvm-svn: 91313
2009-12-14 19:24:11 +00:00
20ac87de13
add Thumb2 atomic and memory barrier instruction definitions
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llvm-svn: 91310
2009-12-14 18:56:47 +00:00
3cdb555e0f
whitespace
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llvm-svn: 91307
2009-12-14 18:36:32 +00:00
5e0d2a2df6
ARM memory barrier instructions are not predicable
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llvm-svn: 91305
2009-12-14 18:31:20 +00:00
9d6410d040
add ldrexd/strexd instructions
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llvm-svn: 91284
2009-12-14 17:02:55 +00:00
8f3c70e909
atomic binary operations up to 32-bits wide.
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llvm-svn: 91260
2009-12-14 04:22:04 +00:00
8f9a3ac12c
Framework for atomic binary operations. The emitter for the pseudo instructions
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just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.
llvm-svn: 91200
2009-12-12 01:40:06 +00:00
22a4ea8690
memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.
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llvm-svn: 91150
2009-12-11 20:29:53 +00:00
098bd1bbea
Store Register Exclusive should leave the source register Inst{3-0} unspecified.
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llvm-svn: 91143
2009-12-11 19:37:26 +00:00
afdddaed55
Update properties.
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llvm-svn: 91140
2009-12-11 18:52:41 +00:00
5c4e99fca6
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
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llvm-svn: 91090
2009-12-11 01:42:04 +00:00
fed78ccfb5
Add instruction encoding for DMB/DSB
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llvm-svn: 91053
2009-12-10 18:35:32 +00:00
53e8854443
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
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llvm-svn: 91003
2009-12-10 00:11:09 +00:00
0c2544fd6b
- Support inline asm 'w' constraint for 128-bit vector types.
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- Also support the 'q' NEON registers asm code.
llvm-svn: 90894
2009-12-08 23:06:22 +00:00
75dfed4fa5
Dynamic stack realignment use of sp register as source/dest register
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in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
llvm-svn: 90724
2009-12-06 22:39:50 +00:00
047a767d74
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
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MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
llvm-svn: 90634
2009-12-05 00:44:40 +00:00
5f9f721e95
remove out of date FIXME.
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llvm-svn: 90490
2009-12-03 21:55:01 +00:00
c831fac043
fix a build problem with VC++, PR5664, patch by Alp Toker!
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llvm-svn: 90419
2009-12-03 06:58:32 +00:00
0bbd3077ce
Recognize canonical forms of vector shuffles where the same vector is used for
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both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
llvm-svn: 90417
2009-12-03 06:40:55 +00:00
a48f44d9ee
improve portability to avoid conflicting with std::next in c++'0x.
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Patch by Howard Hinnant!
llvm-svn: 90365
2009-12-03 00:50:42 +00:00
2c3a6c6589
Factor the stack alignment calculations out into a target independent pass.
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No functionality change.
llvm-svn: 90336
2009-12-02 19:30:24 +00:00
36d4dec28a
Thumb1 exception handling setjmp
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llvm-svn: 90246
2009-12-01 18:10:36 +00:00
86fc920742
For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
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llvm-svn: 90243
2009-12-01 17:37:06 +00:00
ee536b0ea4
For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
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For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.
Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
2009-12-01 00:02:02 +00:00
505ddaa4dc
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
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for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
llvm-svn: 90144
2009-11-30 18:35:03 +00:00
Jakob Stoklund Olesen