b975bebec1
support for >4G stack frames
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llvm-svn: 36425
2007-04-25 04:30:24 +00:00
9bd98ea4c1
support > 4G stack objects
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llvm-svn: 36422
2007-04-25 04:20:54 +00:00
f73d215023
Fix a bug introduced with my previous patch, where it didn't correctly handle
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instructions which replace themselves when FI's are rewritten (common on ppc).
This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll
llvm-svn: 35789
2007-04-09 01:19:33 +00:00
0df5357436
Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308:
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some instructions can have multiple frame indices in them. If this happens,
rewrite all of them.
llvm-svn: 35785
2007-04-09 00:46:10 +00:00
c1b21857a4
If target decides to create an emergency spill slot, make sure it's closest to SP or frame pointer.
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llvm-svn: 34965
2007-03-06 10:02:38 +00:00
105fb1e0dd
Delete register scavenger when done with it.
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llvm-svn: 34786
2007-03-01 10:23:33 +00:00
31215d1395
Interface clean up.
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llvm-svn: 34772
2007-03-01 02:25:51 +00:00
b5582bf984
add a newline at end of file
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llvm-svn: 34735
2007-02-28 06:42:11 +00:00
e8af69632f
Make requiresRegisterScavenging determination on a per MachineFunction basis.
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llvm-svn: 34711
2007-02-28 00:59:19 +00:00
589ba3964b
MRegisterInfo disowns RegScavenger. It's immutable.
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llvm-svn: 34706
2007-02-28 00:17:36 +00:00
e50a994cba
Let MRegisterInfo now owns RegScavenger.
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llvm-svn: 34691
2007-02-27 21:10:33 +00:00
ca25c0ee0d
forward() should not increment internal iterator. Its client may insert instruction between now and next forward() call.
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llvm-svn: 34649
2007-02-27 01:58:48 +00:00
1e56453585
First potential client of register scavenger.
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llvm-svn: 34516
2007-02-23 01:11:26 +00:00
c56315c2b5
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
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for debugging and exception handling.
llvm-svn: 33550
2007-01-26 21:22:28 +00:00
ae4ea45eaf
Added a MRegisterInfo hook that tells PEI the target is responsible for
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rounding the stack frame to a multiple of stack alignment.
llvm-svn: 33504
2007-01-25 22:12:41 +00:00
6730e12ae4
PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary.
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llvm-svn: 33460
2007-01-23 09:38:11 +00:00
887f75ac0a
Remove an unused variable.
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llvm-svn: 33396
2007-01-20 09:21:54 +00:00
7ab6fa3a67
We not align the final stack slot but instead let the target do so in emitPrologue(). Each target can make adjustments to the stack frame and re-align the stack as it deem appropriate. Do not align it twice which can end up wasting stack space.
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llvm-svn: 33387
2007-01-20 02:07:13 +00:00
92484c2aa4
- Fixing naming inconsistency: calleesave -> calleesaved.
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- Make use of spillCalleeSavedRegisters() and restoreCalleeSavedRegisters().
llvm-svn: 32822
2007-01-02 21:31:15 +00:00
c41ed4e0e1
Initialize {Min|Max}CSFrameIndex properly.
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llvm-svn: 32299
2006-12-07 02:25:34 +00:00
bcf1b4120f
TargetRegisterClass specifies the desired spill alignment. However, it cannot be honored if stack alignment is smaller.
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llvm-svn: 30648
2006-09-28 18:52:32 +00:00
d31f55c236
PEI now place callee save spills closest to the address pointed to by the
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incoming stack. This allows X86 backend to use push / pop in epilogue /
prologue.
llvm-svn: 30636
2006-09-28 00:10:27 +00:00
5405c06737
Rename function. It's determining which callee-save registers to save.
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llvm-svn: 30616
2006-09-26 22:29:31 +00:00
3d27be1333
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
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llvm-svn: 29911
2006-08-27 12:54:02 +00:00
fb96c74874
Tidy up.
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llvm-svn: 29888
2006-08-25 22:56:30 +00:00
92206f9404
Consolidate callee saved register information so that it can me used by debug
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information and exception handling.
llvm-svn: 29881
2006-08-25 19:45:51 +00:00
e097e6f7c7
Shave another 27K off libllvmgcc.dylib with visibility hidden
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llvm-svn: 28973
2006-06-28 22:17:39 +00:00
fe211deedf
Remove dead variable
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llvm-svn: 28253
2006-05-12 18:02:04 +00:00
2d7298c362
Foundation for call frame information.
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llvm-svn: 27491
2006-04-07 16:34:46 +00:00
b710a81e54
The stack alignment is now computed dynamically, just verify it is correct.
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llvm-svn: 27380
2006-04-03 21:39:57 +00:00
629ba44e50
Always compute max align.
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llvm-svn: 24227
2005-11-06 17:43:20 +00:00
3ee3e69556
Add the necessary support to the ISel to allow targets to codegen the new
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alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.
llvm-svn: 24224
2005-11-06 09:00:38 +00:00
2e794c9198
now that we have a reg class to spill with, get this info from the regclass
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llvm-svn: 23559
2005-09-30 17:19:22 +00:00
51878189c5
Now that we have getCalleeSaveRegClasses() info, use it to pass the register
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class into the spill/reload methods. Targets can now rely on that argument.
llvm-svn: 23556
2005-09-30 16:59:07 +00:00
5a6199f387
Change this code ot pass register classes into the stack slot spiller/reloader
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code. PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.
llvm-svn: 23536
2005-09-30 01:29:00 +00:00
46d4c75cd1
Fix a bug in my previous patch that was using the wrong iterator. This fixes
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Olden/bisort among others.
llvm-svn: 23124
2005-08-29 00:10:46 +00:00
d4f43f7967
Make this code safe for when loadRegFromStackSlot inserts multiple instructions.
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llvm-svn: 23108
2005-08-26 22:18:32 +00:00
468b9577b6
When inserting callee-save register reloads, make sure to skip over any
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terminator instructions before the 'ret' in case the target has a
multi-instruction return sequence.
llvm-svn: 22041
2005-05-15 03:09:58 +00:00
f6fb5e91b2
Tolerate instrs with extra args
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llvm-svn: 21982
2005-05-13 21:07:15 +00:00
835702a094
Remove trailing whitespace
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llvm-svn: 21420
2005-04-21 22:36:52 +00:00
fb5614506e
Simplify/speedup the PEI by not having to scan for uses of the callee saved
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registers. This information is computed directly by the register allocator
now.
llvm-svn: 19795
2005-01-23 23:13:12 +00:00
ef2de322c6
Speed this up a bit by making ModifiedRegs a vector<char> not vector<bool>
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llvm-svn: 19787
2005-01-23 21:45:01 +00:00
52c97fbea9
Implicitly defined registers can clobber callee saved registers too!
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This fixes the return-address-not-being-saved problem in the Alpha backend.
llvm-svn: 19741
2005-01-22 00:49:16 +00:00
f840289291
Add an assertion that would have made more sense to duraid
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llvm-svn: 19704
2005-01-19 21:32:07 +00:00
c9dec3ae70
Put this change back in after testing from Reid proved its innocence. getSpillSize now returns value in bits
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llvm-svn: 16102
2004-08-29 22:00:24 +00:00
c561fc3731
Back out change to divide getSpillSize by 8 until I figure out why it breaks x86, which has register sizes in bits.
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llvm-svn: 16073
2004-08-27 16:48:24 +00:00
fa2bf42539
Register sizes are in bits, not bytes
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llvm-svn: 16070
2004-08-27 04:28:10 +00:00
36ba4bb042
Register info alignment is in bits, frame object alignment is (currently) in
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bytes.
llvm-svn: 15970
2004-08-21 20:04:59 +00:00
f76ccd43b8
Now that we have per-register spill size/alignment info, remove more uses
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of getRegClass
llvm-svn: 15967
2004-08-21 19:45:10 +00:00
c66f27fd29
Stop using CreateStackObject(RegClass*)
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llvm-svn: 15775
2004-08-15 22:02:22 +00:00
Chris Lattner