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3 Commits

Author SHA1 Message Date
Matt Arsenault f333736757 AMDGPU: Remove SGPRSpillVGPRDefinedSet hack 
These VGPRs should be reserved and therefore do not need "correct"
liveness. They should not have undef uses, which can still cause
issues.
 2020-12-16 21:33:35 -05:00
Jay Foad 58de4b2053 [AMDGPU] Use pseudo instructions for readlane/writelane 
This reverts r227987 "R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2".

All the codegen changes are caused by the post-RA scheduler no longer
treating readlane/writelane as scheduling barriers due to having
unmodelled side effects. (The pseudos are hasSideEffects = 0, but the
real instructions are hasSideEffects = ? which TableGen conservatively
treats as 1.)

Differential Revision: https://reviews.llvm.org/D90401
 2020-10-29 16:00:53 +00:00
Carl Ritson 4a7de36afc [AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills 
Always prefer to clobber input SGPRs and restore them after the
spill.  This applies to both spills to VGPRs and scratch.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D81914
 2020-06-20 12:10:47 +09:00