18484de34b 
								
							 
						 
						
							
							
								
								[Hexagon] Update more testcases  
							
							... 
							
							
							
							llvm-svn: 326830 
							
						 
						
							2018-03-06 19:15:58 +00:00  
				
					
						
							
							
								 
						
							
								a72fad980c 
								
							 
						 
						
							
							
								
								[Hexagon] Replace instruction definitions with auto-generated ones  
							
							... 
							
							
							
							llvm-svn: 294753 
							
						 
						
							2017-02-10 15:33:13 +00:00  
				
					
						
							
							
								 
						
							
								b8575b14be 
								
							 
						 
						
							
							
								
								[Hexagon] Adding some codegen tests and updating some to match spec.  
							
							... 
							
							
							
							llvm-svn: 239690 
							
						 
						
							2015-06-13 21:46:39 +00:00  
				
					
						
							
							
								 
						
							
								be8c453d58 
								
							 
						 
						
							
							
								
								[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.  
							
							... 
							
							
							
							llvm-svn: 239161 
							
						 
						
							2015-06-05 16:00:11 +00:00  
				
					
						
							
							
								 
						
							
								348efdbd36 
								
							 
						 
						
							
							
								
								Shouldn't be XFAIL'ed.  
							
							... 
							
							
							
							llvm-svn: 239103 
							
						 
						
							2015-06-04 21:49:43 +00:00  
				
					
						
							
							
								 
						
							
								c40be85adc 
								
							 
						 
						
							
							
								
								Revert r239095 incorrect test tree.  
							
							... 
							
							
							
							llvm-svn: 239102 
							
						 
						
							2015-06-04 21:32:42 +00:00  
				
					
						
							
							
								 
						
							
								803e506fec 
								
							 
						 
						
							
							
								
								Hexagon: Pass to replace tranfer/copy instructions into combine instruction  
							
							... 
							
							
							
							where possible.
llvm-svn: 181817 
							
						 
						
							2013-05-14 18:54:06 +00:00  
				
					
						
							
							
								 
						
							
								f4e324f4fb 
								
							 
						 
						
							
							
								
								Hexagon: Add encoding bits to the TFR64 instructions.  
							
							... 
							
							
							
							Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.
llvm-svn: 176499 
							
						 
						
							2013-03-05 18:42:28 +00:00  
				
					
						
							
							
								 
						
							
								90295156d8 
								
							 
						 
						
							
							
								
								Use multiclass to define store instructions with base+immediate offset  
							
							... 
							
							
							
							addressing mode and immediate stored value.
llvm-svn: 169408 
							
						 
						
							2012-12-05 19:32:03 +00:00  
				
					
						
							
							
								 
						
							
								4d8986af12 
								
							 
						 
						
							
							
								
								Porting Hexagon MI Scheduler to the new API.  
							
							... 
							
							
							
							Change current Hexagon MI scheduler to use new converging
scheduler. Integrates DFA resource model into it.
llvm-svn: 163137 
							
						 
						
							2012-09-04 14:49:56 +00:00  
				
					
						
							
							
								 
						
							
								91856a1f15 
								
							 
						 
						
							
							
								
								Enable all Hexagon tests.  
							
							... 
							
							
							
							llvm-svn: 156824 
							
						 
						
							2012-05-15 16:13:12 +00:00  
				
					
						
							
							
								 
						
							
								1d195b9c25 
								
							 
						 
						
							
							
								
								Disable Hexagon test temporarily.  
							
							... 
							
							
							
							There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.
The assert is as follows:
    assert(!MI->isTerminator() && !MI->isLabel() &&
               "Cannot schedule terminators or labels!");
llvm-svn: 154617 
							
						 
						
							2012-04-12 21:06:54 +00:00  
				
					
						
							
							
								 
						
							
								d06df96a7c 
								
							 
						 
						
							
							
								
								VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).  
							
							... 
							
							
							
							This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling.
Patch by Sergei Larin!
llvm-svn: 149547 
							
						 
						
							2012-02-01 22:13:57 +00:00  
				
					
						
							
							
								 
						
							
								9ca2e7293b 
								
							 
						 
						
							
							
								
								Hexagon: Fix a nasty order-of-initialization bug.  
							
							... 
							
							
							
							Reenable the tests.
llvm-svn: 146750 
							
						 
						
							2011-12-16 19:08:59 +00:00  
				
					
						
							
							
								 
						
							
								525ca5fc69 
								
							 
						 
						
							
							
								
								Temporarily disable Hexagon tests.  They are failing on OS X  
							
							... 
							
							
							
							llvm-svn: 146455 
							
						 
						
							2011-12-13 00:33:45 +00:00  
				
					
						
							
							
								 
						
							
								1213a7a57f 
								
							 
						 
						
							
							
								
								Hexagon backend support  
							
							... 
							
							
							
							llvm-svn: 146412 
							
						 
						
							2011-12-12 21:14:40 +00:00