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Commit Graph

Author	SHA1	Message	Date
Dmitry Preobrazhensky	2713495318	[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers See bug 35561: https://bugs.llvm.org/show_bug.cgi?id=35561 This patch also affects implementation of SGPR and VGPR registers though changes are cosmetic. Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41437 llvm-svn: 321359	2017-12-22 15:18:06 +00:00
Artem Tamazov	212a251c8d	[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers. Differential Revision: http://reviews.llvm.org/D20476 llvm-svn: 270552	2016-05-24 12:05:16 +00:00

Author

SHA1

Message

Date

Dmitry Preobrazhensky

2713495318

[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers

See bug 35561: https://bugs.llvm.org/show_bug.cgi?id=35561

This patch also affects implementation of SGPR and VGPR registers though changes are cosmetic.

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41437

llvm-svn: 321359

2017-12-22 15:18:06 +00:00

Artem Tamazov

212a251c8d

[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.

Differential Revision: http://reviews.llvm.org/D20476

llvm-svn: 270552

2016-05-24 12:05:16 +00:00

2 Commits