2 Commits

Author	SHA1	Message	Date
Craig Topper	ad923edfc1	[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump ... This makes the llvm-objdump output much more readable and closer to binutils objdump. This builds on D76591 It requires changing the OperandType for certain immediates to "OPERAND_PCREL" so tablegen will generate code to pass the instruction's address. This means we can't do the generic check on these instructions in verifyInstruction any more. Should I add it back with explicit opcode checks? Or should we add a new operand flag to control the passing of address instead of matching the name? Differential Revision: https://reviews.llvm.org/D92147	2020-12-04 10:34:12 -08:00
Simon Cook	2df6a02fd7	[RISCV] Implement evaluateBranch ... This implements the instruction analysis required to print branch targets as part of llvm-objdump's disassembly. Note, this only handles those branches which can be analyzed in a single instruction, a future patch will handle multiple-instruction patterns, such as AUIPC/LUI+JALR instruction pairs. Differential Revision: https://reviews.llvm.org/D77567	2020-04-09 15:11:55 +01:00