5bc8a79e7f
Also use REG_SEQUENCE for VTBX instructions.
...
llvm-svn: 107743
2010-07-07 00:08:54 +00:00
3ed511bc6b
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
...
allocated to consecutive registers.
llvm-svn: 107730
2010-07-06 23:36:25 +00:00
78ad27ca2b
Remove an unused and a pointless variable.
...
llvm-svn: 107131
2010-06-29 13:00:29 +00:00
f1d8304fe3
Eliminate unnecessary uses of getZExtValue().
...
llvm-svn: 106279
2010-06-18 14:22:04 +00:00
01ac8f9fc0
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
...
now, so there's no need to disable them.
llvm-svn: 106155
2010-06-16 21:34:01 +00:00
d8a9a04739
For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
...
VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized. That is pretty awful, but I guess it
makes sense for other targets. Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.
llvm-svn: 105439
2010-06-04 00:04:02 +00:00
d679ff7330
Early implementation of tail call for ARM.
...
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
llvm-svn: 105413
2010-06-03 21:09:53 +00:00
84511e1526
Clean up 80 column violations. No functional change.
...
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
b6112e8706
Add the cc_out operand for t2RSBrs instructions. I missed this when I changed
...
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.
llvm-svn: 104907
2010-05-28 00:27:15 +00:00
8d042c0269
Fix a few places that depended on the numeric value of subreg indices.
...
Add assertions in places that depend on consecutive indices.
llvm-svn: 104510
2010-05-24 17:13:28 +00:00
6c47d6423c
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
...
from ARMRegisterInfo.h
llvm-svn: 104508
2010-05-24 16:54:32 +00:00
e89f5ae9d4
Target instruction selection should copy memoperands.
...
llvm-svn: 104110
2010-05-19 06:06:09 +00:00
3d98b996ff
Turn on -neon-reg-sequence by default.
...
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
llvm-svn: 103960
2010-05-17 19:51:20 +00:00
298e6b82eb
Model vst lane instructions with REG_SEQUENCE.
...
llvm-svn: 103898
2010-05-16 03:27:48 +00:00
9e688cbcc9
Model 128-bit vld lane with REG_SEQUENCE.
...
llvm-svn: 103868
2010-05-15 07:53:37 +00:00
0cbd11dfb2
Model 64-bit lane vld with REG_SEQUENCE.
...
llvm-svn: 103851
2010-05-15 01:36:29 +00:00
cb78e5558b
Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
...
llvm-svn: 103833
2010-05-14 22:54:52 +00:00
cfa7d02d6e
Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
...
llvm-svn: 103790
2010-05-14 18:54:59 +00:00
ca21cc8b13
Fix comments.
...
llvm-svn: 103749
2010-05-14 00:21:45 +00:00
e276c18385
Model some vst3 and vst4 with reg_sequence.
...
llvm-svn: 103453
2010-05-11 01:19:40 +00:00
630063aa0d
Model some vld3 instructions with REG_SEQUENCE.
...
llvm-svn: 103437
2010-05-10 21:26:24 +00:00
c2ae5f546f
Model vld2 / vst2 with reg_sequence.
...
llvm-svn: 103411
2010-05-10 17:34:18 +00:00
f765e1f34a
Add a missing break statement to fix unintentional fall-through
...
(replacing the previous patch for the same issue).
llvm-svn: 103183
2010-05-06 16:05:26 +00:00
5e3cccb1e4
Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
...
llvm-svn: 103181
2010-05-06 15:32:49 +00:00
d85631e700
Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
...
llvm-svn: 103104
2010-05-05 18:28:36 +00:00
8e6b40a881
With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.
...
llvm-svn: 103047
2010-05-04 20:39:49 +00:00
825cb299cd
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
...
extraction. This fixes PR5998.
llvm-svn: 102144
2010-04-22 23:24:18 +00:00
21cea8ac2e
Use const qualifiers with TargetLowering. This eliminates several
...
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
llvm-svn: 101635
2010-04-17 15:26:15 +00:00
3da64f7672
Use getAL() rather than a major constant.
...
llvm-svn: 101446
2010-04-16 05:46:06 +00:00
f7f97b4bbd
Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
...
llvm-svn: 101410
2010-04-15 22:20:34 +00:00
1ba1428577
ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
...
llvm is generating poor code for dynamic alloca, I'll fix that later.
llvm-svn: 101383
2010-04-15 18:42:28 +00:00
59f75bba24
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
...
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
llvm-svn: 99309
2010-03-23 18:54:46 +00:00
cc0a2a75a0
Change VST1 instructions for loading Q register values to operate on pairs
...
of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
llvm-svn: 99265
2010-03-23 06:20:33 +00:00
340861d29e
Change VLD1 instructions for loading Q register values to operate on pairs
...
of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
llvm-svn: 99261
2010-03-23 05:25:43 +00:00
c53a1125ff
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
...
corresponding NEON instructions, instead of operation they are currently
used for.
llvm-svn: 99189
2010-03-22 18:13:18 +00:00
ae08a736d6
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
...
with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
llvm-svn: 99095
2010-03-20 22:13:40 +00:00
c0795f8b87
Rename some instructions for consistency and sanity: use "_UPD" suffix for
...
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.
llvm-svn: 99066
2010-03-20 18:35:24 +00:00
c7ba918b84
Revert 98683. It is breaking something in the disassembler.
...
llvm-svn: 98692
2010-03-16 23:01:13 +00:00
c953bca10b
Remove redundant writeback flag from ARM address mode 6. Also remove the
...
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.
llvm-svn: 98683
2010-03-16 21:44:40 +00:00
f98f124a73
Sink InstructionSelect() out of each target into SDISel, and rename it
...
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
llvm-svn: 97555
2010-03-02 06:34:30 +00:00
5e73ff2e3a
Split SelectionDAGISel::IsLegalAndProfitableToFold to
...
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
llvm-svn: 96255
2010-02-15 19:41:07 +00:00
b06015aa69
move target-independent opcodes out of TargetInstrInfo
...
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
2010-02-09 19:54:29 +00:00
6c0fb92c03
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
...
llvm-svn: 93829
2010-01-19 00:44:15 +00:00
8546ec9c14
Patch by David Conrad:
...
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
llvm-svn: 93758
2010-01-18 19:58:49 +00:00
55d2ebda31
Fix an off-by-one error that caused the chain operand to be dropped from Neon
...
vector load-lane and store-lane instructions.
llvm-svn: 93673
2010-01-17 05:58:23 +00:00
ea6f91ff64
Change SelectCode's argument from SDValue to SDNode *, to make it more
...
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
llvm-svn: 92564
2010-01-05 01:24:18 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
a33fc86be3
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
...
llvm-svn: 89542
2009-11-21 06:21:52 +00:00
81a2851bcb
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
...
llvm-svn: 89423
2009-11-20 00:54:03 +00:00
b6c7704a8d
Refactor cmov selection code out to a separate function. No functionality change.
...
llvm-svn: 89396
2009-11-19 21:45:22 +00:00
82adca8373
80 col violation.
...
llvm-svn: 89337
2009-11-19 08:16:50 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
...
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
d1d002a6fe
Support alignment specifier for NEON vld/vst instructions
...
llvm-svn: 86404
2009-11-07 21:25:39 +00:00
b15f4a1cbd
Remove uninteresting and confusing debug output.
...
llvm-svn: 86149
2009-11-05 18:47:09 +00:00
e90a4aa703
Prune unnecessary include.
...
llvm-svn: 85805
2009-11-02 16:58:31 +00:00
b678a56fef
Test commit. Added '.' to the comment line.
...
llvm-svn: 85255
2009-10-27 17:25:15 +00:00
0f55e9ce2e
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
...
llvm-svn: 84813
2009-10-22 00:40:00 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
ad03cf02f6
Remove unused variables to fix build warning.
...
llvm-svn: 84144
2009-10-14 21:40:45 +00:00
c350cdf3b3
Refactor code to select NEON VST intrinsics.
...
llvm-svn: 84122
2009-10-14 18:32:29 +00:00
12b4799787
Refactor code to select NEON VLD intrinsics.
...
llvm-svn: 84117
2009-10-14 17:28:52 +00:00
93117bc499
More refactoring. NEON vst lane intrinsics can share almost all the code for
...
vld lane intrinsics.
llvm-svn: 84110
2009-10-14 16:46:45 +00:00
4145e3ac8d
Refactor code for selecting NEON load lane intrinsics.
...
llvm-svn: 84109
2009-10-14 16:19:03 +00:00
b62d160b3c
More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
...
by creating TargetConstants during instruction selection instead of during
legalization.
llvm-svn: 84042
2009-10-13 22:29:24 +00:00
3b51560ae4
Revise ARM inline assembly memory operands to require the memory address to
...
be in a register. The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb. Radar 7137468.
llvm-svn: 84022
2009-10-13 20:50:28 +00:00
7460e0822f
Fix method name in comment, per Bob Wilson.
...
llvm-svn: 84017
2009-10-13 20:25:58 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
...
llvm-svn: 84009
2009-10-13 18:59:48 +00:00
84e7967fae
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
...
llvm-svn: 83600
2009-10-09 00:01:36 +00:00
c409030838
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
...
llvm-svn: 83598
2009-10-08 23:51:31 +00:00
b851eb356a
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
...
llvm-svn: 83596
2009-10-08 23:38:24 +00:00
38ba47225a
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
...
Also fix some copy-and-paste errors in previous changes.
llvm-svn: 83590
2009-10-08 22:53:57 +00:00
cf54e934f8
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
...
llvm-svn: 83585
2009-10-08 22:27:33 +00:00
c2728f44a9
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
...
llvm-svn: 83568
2009-10-08 18:56:10 +00:00
fac9476589
Clean up some unnecessary initializations.
...
llvm-svn: 83566
2009-10-08 18:52:56 +00:00
4facd965bd
Clean up a comment (indentation was wrong).
...
llvm-svn: 83565
2009-10-08 18:51:31 +00:00
b6b0ab6117
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83526
2009-10-08 05:18:18 +00:00
71387b4b2f
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83518
2009-10-08 00:28:28 +00:00
d4f5670096
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83513
2009-10-08 00:21:01 +00:00
32cc4ec304
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83508
2009-10-07 23:54:04 +00:00
5ef3c6d9f4
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83506
2009-10-07 23:39:57 +00:00
763be1a248
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83502
2009-10-07 22:57:01 +00:00
e7ef4a9a6b
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
...
llvm-svn: 83486
2009-10-07 20:49:18 +00:00
23464866ad
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
...
llvm-svn: 83484
2009-10-07 20:30:08 +00:00
3dcb5377ef
Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
...
llvm-svn: 83482
2009-10-07 18:47:39 +00:00
ab3a9474d6
Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
...
llvm-svn: 83479
2009-10-07 18:09:32 +00:00
6bbefc2f67
Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
...
llvm-svn: 83471
2009-10-07 17:24:55 +00:00
99e80228a9
Rearrange code for selecting vld2 intrinsics. No functionality change.
...
This is just to be more consistent with the forthcoming code for vld3/4.
llvm-svn: 83470
2009-10-07 17:23:09 +00:00
e6b778d5ff
Add codegen support for NEON vld2 operations on quad registers.
...
llvm-svn: 83422
2009-10-06 22:01:59 +00:00
2dd957fff6
Pass the optimization level when constructing the ARM instruction selector.
...
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel. Radar 7250345.
llvm-svn: 82988
2009-09-28 14:30:20 +00:00
7c2b1e71c1
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
...
This should be better than single load from constpool.
llvm-svn: 82948
2009-09-27 23:52:58 +00:00
32f71d714b
Rename getTargetNode to getMachineNode, for consistency with the
...
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
llvm-svn: 82790
2009-09-25 18:54:59 +00:00
d7797754d4
Add support for generating code for vst{234}lane intrinsics.
...
llvm-svn: 80707
2009-09-01 18:51:56 +00:00
da9817cddd
Generate code for vld{234}_lane intrinsics.
...
llvm-svn: 80656
2009-09-01 04:26:28 +00:00
e0636a7aed
Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
...
The instructions can be selected directly from the intrinsics. We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.
llvm-svn: 80117
2009-08-26 17:39:53 +00:00
0939595711
Record variable debug info at ISel time directly.
...
llvm-svn: 79742
2009-08-22 17:12:53 +00:00
232b19c3d5
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
...
llvm-svn: 79625
2009-08-21 12:41:42 +00:00
ce3ff1be8a
Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
...
llvm-svn: 79622
2009-08-21 12:40:50 +00:00
51c7aa04ec
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
...
vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.
llvm-svn: 79579
2009-08-21 00:01:42 +00:00
9a58aff837
Indentation.
...
llvm-svn: 79022
2009-08-14 19:01:37 +00:00
cce31f6831
During legalization, change Neon vdup_lane operations from shuffles to
...
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
llvm-svn: 78993
2009-08-14 05:08:32 +00:00
55f1c09e31
Push LLVMContexts through the IntegerType APIs.
...
llvm-svn: 78948
2009-08-13 21:58:54 +00:00
bb2af3555c
Shrink Thumb2 movcc instructions.
...
llvm-svn: 78790
2009-08-12 05:17:19 +00:00
f042eadd1e
Add missing chain operands for VLD* and VST* instructions.
...
Set "mayLoad" and "mayStore" on the load/store instructions.
llvm-svn: 78761
2009-08-12 00:49:01 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
...
llvm-svn: 78745
2009-08-11 23:00:31 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
...
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
3606467709
Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
...
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.
llvm-svn: 78658
2009-08-11 08:52:18 +00:00
12842f9865
Use vAny type to get rid of Neon intrinsics that differed only in whether
...
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
733a64db57
Fix a bug where DAGCombine was producing an illegal ConstantFP
...
node after legalize, and remove the workaround code from the
ARM backend.
llvm-svn: 78615
2009-08-10 23:15:10 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
...
llvm-svn: 78594
2009-08-10 20:25:59 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
...
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
e2231070ff
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
...
so I generalized the class for VTRN in the .td file to handle all 3 of them.
llvm-svn: 78460
2009-08-08 06:13:25 +00:00
db46af0461
Implement Neon VTRN instructions. For now, anyway, these are selected
...
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
llvm-svn: 78459
2009-08-08 05:53:00 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
...
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
0127031c20
Implement Neon VST[234] operations.
...
llvm-svn: 78330
2009-08-06 18:47:44 +00:00
488db94e7b
Neon does not actually have VLD{234}.64 instructions.
...
These operations will have to be synthesized from other instructions.
llvm-svn: 78263
2009-08-06 00:24:27 +00:00
20f79e321e
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
...
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
llvm-svn: 78136
2009-08-05 00:49:09 +00:00
f307e0bd6d
Lower CONCAT_VECTOR during legalization instead of matching it during isel.
...
Add a testcase.
llvm-svn: 77992
2009-08-03 20:36:38 +00:00
e6e8289d72
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
...
llvm-svn: 77764
2009-08-01 01:43:45 +00:00
5aae45fb6f
Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode.
...
llvm-svn: 77632
2009-07-30 22:45:52 +00:00
79c079b478
Cleanup and include code selection for some frame index cases.
...
llvm-svn: 77622
2009-07-30 18:56:48 +00:00
faede73a32
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
...
llvm-svn: 77172
2009-07-26 23:59:01 +00:00
edb4a70325
Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.
...
llvm-svn: 77011
2009-07-24 23:12:02 +00:00
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
...
llvm-svn: 76919
2009-07-24 00:16:18 +00:00
e270d4a4dd
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
...
llvm-svn: 76803
2009-07-22 22:03:29 +00:00
1ec4396ee3
Eliminate a redudant check Eli pointed out.
...
llvm-svn: 76762
2009-07-22 18:08:05 +00:00
0d8b0cf3b8
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
...
llvm-svn: 76520
2009-07-21 00:31:12 +00:00
802a0b576f
Use t2LDRri12 for frame index loads.
...
llvm-svn: 76424
2009-07-20 15:55:39 +00:00
f39120571b
Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].
...
llvm-svn: 75789
2009-07-15 15:50:19 +00:00
b6b2530000
Move EVER MORE stuff over to LLVMContext.
...
llvm-svn: 75703
2009-07-14 23:09:55 +00:00
95bad85498
Check for PRE_INC and POST_INC.
...
llvm-svn: 75683
2009-07-14 21:29:29 +00:00
4ad7797e1c
hasThumb2() does not mean we are compiling for thumb, must also check isThumb().
...
llvm-svn: 75660
2009-07-14 18:48:51 +00:00
0794c6a083
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
...
llvm-svn: 75360
2009-07-11 07:08:13 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
...
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
7591d02c84
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
...
Note, we are not yet generating these instructions.
llvm-svn: 75181
2009-07-09 22:21:59 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
...
llvm-svn: 75067
2009-07-08 23:10:31 +00:00
e3a53c448b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
...
llvm-svn: 75048
2009-07-08 21:03:57 +00:00
fb8d6d5b58
Implement changes from Chris's feedback.
...
Finish converting lib/Target.
llvm-svn: 75043
2009-07-08 20:53:28 +00:00
d0611f9a37
Add Thumb2 movcc instructions.
...
llvm-svn: 74946
2009-07-07 20:39:03 +00:00
b24e51e2d9
Add some more Thumb2 multiplication instructions.
...
llvm-svn: 74889
2009-07-07 01:17:28 +00:00
8ecd7eb3f7
Sign extending pre/post indexed loads.
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llvm-svn: 74736
2009-07-02 23:16:11 +00:00
84c6cda2ef
Thumb2 pre/post indexed loads.
...
llvm-svn: 74696
2009-07-02 07:28:31 +00:00
d9c55368e7
Factor out ARM indexed load matching code.
...
llvm-svn: 74681
2009-07-02 01:23:32 +00:00
deb35afd23
Add a new addressing mode for NEON load/store instructions.
...
llvm-svn: 74658
2009-07-01 23:16:05 +00:00
a83100f687
Thumb-2 load and store double description. But nothing yet creates them.
...
llvm-svn: 74566
2009-06-30 22:50:01 +00:00
27303cde82
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
...
llvm-svn: 74543
2009-06-30 18:04:13 +00:00
b23b50d54d
Implement Thumb2 ldr.
...
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
eab9ca7ea6
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
99152f3a2c
Split thumb-related stuff into separate classes.
...
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo
llvm-svn: 74329
2009-06-26 21:28:53 +00:00
8d21e9c4e6
Code clean up.
...
llvm-svn: 73986
2009-06-23 19:38:34 +00:00
e379107cdc
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
...
llvm-svn: 73975
2009-06-23 18:14:38 +00:00
2e076c4e02
Add support for ARM's Advanced SIMD (NEON) instruction set.
...
This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
360eef0782
Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops
...
predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.
llvm-svn: 73887
2009-06-22 17:29:13 +00:00
02bb33c58d
Initial support for some Thumb2 instructions.
...
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
llvm-svn: 73622
2009-06-17 18:13:58 +00:00
3708883bfe
Revert hunk commited by accident
...
llvm-svn: 73097
2009-06-08 22:57:18 +00:00
77d1943637
The attached patches implement most of the ARM AAPCS-VFP hard float
...
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
llvm-svn: 73095
2009-06-08 22:53:56 +00:00
a2c462bbe9
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
...
llvm-svn: 72105
2009-05-19 05:53:42 +00:00
fde2110aa9
PR2985 / <rdar://problem/6584986>
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When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
llvm-svn: 68545
2009-04-07 20:34:09 +00:00
904f14663d
tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode.
...
llvm-svn: 67765
2009-03-26 19:09:01 +00:00
844deb73f4
fix PR3538 for ARM.
...
llvm-svn: 64384
2009-02-12 17:38:23 +00:00
ab8e4425a3
Eliminate remaining non-DebugLoc version of getTargetNode.
...
llvm-svn: 63951
2009-02-06 19:16:40 +00:00
2c4cf2752d
get rid of some non-DebugLoc getTargetNode variants.
...
llvm-svn: 63909
2009-02-06 02:08:06 +00:00
9f3f72f144
Get rid of one more non-DebugLoc getNode and
...
its corresponding getTargetNode. Lots of
caller changes.
llvm-svn: 63904
2009-02-06 01:31:28 +00:00
619ef48a52
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
...
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
llvm-svn: 62275
2009-01-15 19:20:50 +00:00
d5021730c8
Preliminary ARM debug support based on patch by Mikael of FlexyCore.
...
llvm-svn: 60851
2008-12-10 21:54:21 +00:00
810daf7e93
Update a comment.
...
llvm-svn: 60484
2008-12-03 17:10:41 +00:00
f14b77ebf1
Eliminate the ISel priority queue, which used the topological order for a
...
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
llvm-svn: 58748
2008-11-05 04:14:16 +00:00
ce2a938186
Have TableGen emit setSubgraphColor calls under control of a -gen-debug
...
flag. Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like. This really helps when debugging instruction selection.
llvm-svn: 58278
2008-10-27 21:56:29 +00:00
2c836cf187
Avoid creating two TargetLowering objects for each target.
...
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.
llvm-svn: 57016
2008-10-03 16:55:19 +00:00
bc0d0eccf3
Cosmetic.
...
llvm-svn: 56299
2008-09-18 07:24:33 +00:00
effb894453
Rename ConstantSDNode::getValue to getZExtValue, for consistency
...
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
f304a7aa4d
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
...
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
abfdf928d8
disallow direct access to SDValue::ResNo, provide a getter instead
...
llvm-svn: 55394
2008-08-26 22:36:50 +00:00
eb0cee91f6
Move the point at which FastISel taps into the SelectionDAGISel
...
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
llvm-svn: 55219
2008-08-23 02:25:05 +00:00
d3582c9bda
Simplify SelectRoot's interface, and factor out some common code
...
from all targets.
llvm-svn: 55124
2008-08-21 16:36:34 +00:00
2ce6f2ad5e
Rename SDOperand to SDValue.
...
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
1705968102
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
...
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
llvm-svn: 53728
2008-07-17 19:10:17 +00:00
56e3f63ec5
Add explicit keywords.
...
llvm-svn: 53179
2008-07-07 18:00:37 +00:00
0711d68fa7
Split scheduling from instruction selection.
...
llvm-svn: 52923
2008-06-30 20:45:06 +00:00
13237ac3b9
Wrap MVT::ValueType in a struct to get type safety
...
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
llvm-svn: 52044
2008-06-06 12:08:01 +00:00
2cb9068c78
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
...
llvm-svn: 46724
2008-02-04 23:06:48 +00:00
1770fb883b
explicitly include Compiler.h instead of getting it from tblgen in the middle of a class.
...
llvm-svn: 46676
2008-02-03 05:43:57 +00:00
e99faac423
don't do ReplaceUses on a result that doesn't exist.
...
llvm-svn: 46673
2008-02-03 03:20:59 +00:00
efd142a920
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
...
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
llvm-svn: 46659
2008-02-02 04:07:54 +00:00
47a7d6fafe
Factor the addressing mode and the load/store VT out of LoadSDNode
...
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
llvm-svn: 46538
2008-01-30 00:15:11 +00:00
a10fff51d9
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
...
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
llvm-svn: 45467
2007-12-31 04:13:23 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
...
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
a160361c85
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
...
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
llvm-svn: 42762
2007-10-08 18:33:35 +00:00
9d41b311fb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
...
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
7e90b11550
Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
...
llvm-svn: 37896
2007-07-05 07:15:27 +00:00
0f7cbe8370
Add PredicateOperand to all ARM instructions that have the condition field.
...
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
1c1082133c
match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
...
llvm-svn: 36660
2007-05-03 00:32:00 +00:00
9bb01c9f4f
Fix naming inconsistencies.
...
llvm-svn: 35163
2007-03-19 07:48:02 +00:00
ee2763f76f
Special LDR instructions to load from non-pc-relative constantpools. These are
...
rematerializable. Only used for constant generation for now.
llvm-svn: 35162
2007-03-19 07:20:03 +00:00
72a8bcf238
AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2 ]
...
llvm-svn: 35088
2007-03-13 21:05:54 +00:00
62aef236de
Get rid of references to iostream.
...
llvm-svn: 34009
2007-02-07 21:18:32 +00:00
a974031ebd
Select add FI, c correctly.
...
llvm-svn: 33960
2007-02-06 09:11:20 +00:00
650d0672f7
- Store val, [sp, c] must be selected to tSTRsp.
...
- If c does not fit in the offset field, materialize sp + c into a register
using tADDhirr.
llvm-svn: 33944
2007-02-06 00:22:06 +00:00
1cd3c0efb8
Change the operand orders to t_addrmode_s* to make it easier to morph
...
instructions that use these address modes to instructions that use
t_addrmode_sp.
llvm-svn: 33651
2007-01-30 02:35:32 +00:00
1526ba50d9
Use PC relative ldr to load from a constantpool in Thumb mode.
...
llvm-svn: 33484
2007-01-24 08:53:17 +00:00
8942551dee
Allow [ fi#c, imm ] as ARM load / store addresses.
...
llvm-svn: 33474
2007-01-24 02:45:25 +00:00
139edae4a2
Various Thumb mode load / store isel bug fixes.
...
llvm-svn: 33472
2007-01-24 02:21:22 +00:00
c0b7366cf9
- Reorg Thumb load / store instructions. Combine each rr and ri pair of
...
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
address is not an add, materialize a 0 immediate into a register and use
it as the offset field.
llvm-svn: 33470
2007-01-23 22:59:13 +00:00
10043e215b
ARM backend contribution from Apple.
...
llvm-svn: 33353
2007-01-19 07:51:42 +00:00
c4235e5521
Build constants using instructions mov/orr or mvn/eor.
...
llvm-svn: 33141
2007-01-12 20:35:49 +00:00
7284073ec2
Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64).
...
llvm-svn: 32870
2007-01-04 14:01:38 +00:00
fd68718467
implement missing compares
...
patch by Lauro
bug fixed by me
llvm-svn: 32795
2006-12-31 18:52:39 +00:00
e63b6518fa
For PR950:
...
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
llvm-svn: 32788
2006-12-31 05:55:36 +00:00
64493fb30d
fix comment
...
llvm-svn: 32767
2006-12-29 14:28:12 +00:00
7251e57ff8
Implement SELECT_CC (f32/f64) for ARM.
...
llvm-svn: 32762
2006-12-28 13:11:14 +00:00
3b7544e24c
avoid using a constant table when a constant can be used inline
...
llvm-svn: 32580
2006-12-14 18:58:37 +00:00
67d1c8ae0e
more general matching of the MVN instruction
...
llvm-svn: 32484
2006-12-12 17:10:13 +00:00
470d61d82c
don't use "ordinary" addressing mode 1 when mvn is appropriate
...
llvm-svn: 32482
2006-12-12 14:03:29 +00:00
9fa0a26808
use MVN to handle small negative constants
...
llvm-svn: 32459
2006-12-12 01:03:11 +00:00
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
...
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
b5dee63958
expand memmove and memcpy
...
llvm-svn: 32226
2006-12-05 17:57:23 +00:00
96fd6447c7
add support for the "r" asm constraint
...
patch by Lauro Ramos Venancio
llvm-svn: 32224
2006-12-05 17:37:31 +00:00
5f7ab1b964
implement load effective address similar to the alpha backend
...
remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
6cd0909da7
Match tblegen changes.
...
llvm-svn: 31571
2006-11-08 20:34:28 +00:00
708cb60588
initial implementation of addressing mode 2
...
TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
ac8668d62f
move ARMCondCodeToString to ARMAsmPrinter.cpp
...
remove unused variables from lowerCall
llvm-svn: 31378
2006-11-02 15:00:02 +00:00
0d41d19427
All targets expand BR_JT for now.
...
llvm-svn: 31294
2006-10-30 08:02:39 +00:00
a23166d6a4
initial support for frame pointers
...
llvm-svn: 31197
2006-10-26 13:31:26 +00:00
bd29281e97
expand ISD::VACOPY
...
llvm-svn: 31170
2006-10-24 20:15:21 +00:00
cd5f662c7b
expand ISD::MEMSET
...
llvm-svn: 31137
2006-10-23 20:08:22 +00:00
e0fc4dfc22
For PR950:
...
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
llvm-svn: 31063
2006-10-20 07:07:24 +00:00
3c563c5072
expand SIGN_EXTEND_INREG
...
llvm-svn: 31046
2006-10-19 12:06:50 +00:00
b260306625
expand brind so that we don't have to implement jump tables right now
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llvm-svn: 31045
2006-10-19 10:56:43 +00:00
b21e8d2e12
implement CallingConv::Fast as CallingConv::C
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llvm-svn: 31034
2006-10-18 12:03:07 +00:00
ba8f296167
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
...
llvm-svn: 31014
2006-10-17 21:05:33 +00:00
19398ec86e
initial implementation of addressing mode 5
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llvm-svn: 31002
2006-10-17 18:04:53 +00:00
f719c5f43d
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
...
llvm-svn: 30987
2006-10-16 21:10:32 +00:00
2b7f635951
expand ISD::BRCOND
...
llvm-svn: 30963
2006-10-14 17:59:54 +00:00
4c1baf1528
fix some fp condition codes
...
use non trapping comparison instructions
llvm-svn: 30962
2006-10-14 13:42:53 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
79d9807c87
implement calls to functions that return long
...
llvm-svn: 30929
2006-10-13 16:47:22 +00:00
3874a168d0
implement unordered floating point compares
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llvm-svn: 30928
2006-10-13 13:14:59 +00:00
8429e1f6c3
uint <-> double conversion
...
llvm-svn: 30862
2006-10-10 20:38:57 +00:00
57d109fb08
add double <-> int conversion
...
llvm-svn: 30858
2006-10-10 18:55:14 +00:00
d1a4ea41c9
compare doubles
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llvm-svn: 30856
2006-10-10 16:33:47 +00:00
d15c892433
initial support for fp compares. Unordered compares not implemented yet
...
llvm-svn: 30854
2006-10-10 12:56:00 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
e4c3276afc
expand ISD::SELECT
...
llvm-svn: 30829
2006-10-09 16:28:33 +00:00
41730922bb
expand ISD::EXTLOAD
...
llvm-svn: 30827
2006-10-09 14:13:40 +00:00
b50938866b
implement FUITOS and FUITOD
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llvm-svn: 30803
2006-10-07 14:24:52 +00:00
aa2a12f1a2
add optional input flag to FMRRD
...
llvm-svn: 30774
2006-10-06 20:33:26 +00:00
671f25281d
add support for calling functions that return double
...
llvm-svn: 30771
2006-10-06 19:10:05 +00:00
ef01656ea4
fix some bugs affecting functions with no arguments
...
llvm-svn: 30767
2006-10-06 17:26:30 +00:00
5fe7909e18
add support for calling functions that have double arguments
...
llvm-svn: 30765
2006-10-06 12:50:22 +00:00
df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
decfeca52d
use a const ref for passing the vector to ArgumentLayout
...
llvm-svn: 30756
2006-10-05 17:46:48 +00:00
e04df41ca2
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL
...
implement FMDRR
add support for f64 function arguments
llvm-svn: 30754
2006-10-05 16:48:49 +00:00
68d238801c
Implement floating point constants
...
llvm-svn: 30704
2006-10-03 17:27:58 +00:00
d55c0a41df
fix the names of the 64bit fp register
...
initial support for returning 64bit floating point numbers
llvm-svn: 30692
2006-10-02 19:30:56 +00:00
53f78be49e
add floating point registers
...
implement SINT_TO_FP
llvm-svn: 30673
2006-09-29 21:20:16 +00:00
7b700e517a
more condition codes
...
llvm-svn: 30567
2006-09-21 13:06:26 +00:00
0c71a5adc8
if a constant can't be an immediate, add it to the constant pool
...
llvm-svn: 30566
2006-09-21 11:29:52 +00:00
3130a756ef
add shifts to addressing mode 1
...
llvm-svn: 30291
2006-09-13 12:09:43 +00:00
9a083a4121
Reflects MachineConstantPoolEntry changes.
...
llvm-svn: 30279
2006-09-12 21:04:05 +00:00
bccf9c2f1b
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
...
llvm-svn: 30261
2006-09-11 19:23:32 +00:00
e45a79a9e2
partial implementation of the ARM Addressing Mode 1
...
llvm-svn: 30252
2006-09-11 17:25:40 +00:00
8386105f3f
add support for returning 64bit values
...
llvm-svn: 30103
2006-09-04 19:05:01 +00:00
5328ba96e1
add the SETULT condition code
...
llvm-svn: 30067
2006-09-03 13:19:16 +00:00
c585b6919b
add more condition codes
...
llvm-svn: 30056
2006-09-02 20:24:25 +00:00
61413a3d72
Select() no longer require Result operand by reference.
...
llvm-svn: 29898
2006-08-26 05:34:46 +00:00
98dc23fd1f
use @ for comments
...
store LR in an arbitrary stack slot
add support for writing varargs functions
llvm-svn: 29876
2006-08-25 17:55:16 +00:00
29e4875f57
add the "eq" condition code
...
implement a movcond instruction
llvm-svn: 29857
2006-08-24 17:19:08 +00:00
fe03fe9bf4
create a generic bcond instruction that has a conditional code argument
...
llvm-svn: 29856
2006-08-24 16:13:15 +00:00
e08b9853cc
initial support for branches
...
llvm-svn: 29854
2006-08-24 13:45:55 +00:00
d0dee77718
initial support for select
...
llvm-svn: 29802
2006-08-21 22:00:32 +00:00
8a675a5d09
call computeRegisterProperties
...
llvm-svn: 29780
2006-08-20 01:49:49 +00:00
c3ed77e1b9
add a "load effective address"
...
llvm-svn: 29748
2006-08-17 17:09:40 +00:00
bf8e751488
Declare the callee saved regs
...
Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
157971b04a
select code like
...
ldr rx, [ry, #offset]
llvm-svn: 29664
2006-08-14 19:01:24 +00:00
ed728e8dc9
Eliminate use of getNode that takes a vector.
...
llvm-svn: 29614
2006-08-11 17:38:39 +00:00
c62914880f
elimiante use of getNode that takes vector of operands.
...
llvm-svn: 29612
2006-08-11 17:22:35 +00:00
bd1c5a8fb8
Match tablegen changes.
...
llvm-svn: 29604
2006-08-11 09:08:15 +00:00
f5ce475540
fix the spill code
...
llvm-svn: 29583
2006-08-09 16:41:12 +00:00
39083e7836
initial support for variable number of arguments
...
llvm-svn: 29567
2006-08-08 13:02:29 +00:00
b9d34bd098
Match tablegen isel changes.
...
llvm-svn: 29549
2006-08-07 22:28:20 +00:00
2bcb8c0f05
use a 'register pressure reducing' scheduler
...
make sure only one move is used in a hello world
llvm-svn: 29520
2006-08-04 12:48:42 +00:00
e19f6fde2d
Bug fix: always generate a RET_FLAG in LowerRET
...
fixes ret_null.ll and call.ll
llvm-svn: 29519
2006-08-03 22:50:11 +00:00
a94b9e33af
add and use ARMISD::RET_FLAG
...
llvm-svn: 29499
2006-08-03 17:02:20 +00:00
95035cf001
implement LowerConstantPool and LowerGlobalAddress
...
llvm-svn: 29433
2006-08-01 12:58:43 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
8902fd702b
implement function calling of functions with up to 4 arguments
...
llvm-svn: 29274
2006-07-25 20:17:20 +00:00
75269be065
skeleton of a lowerCall implementation for ARM
...
llvm-svn: 29159
2006-07-16 01:02:57 +00:00
185c5c2bdf
add the memri memory operand
...
this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
e40a7e2aa2
create the raddr addressing mode that matches any register and the frame index
...
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
f6f5aff038
handle the "mov reg1, reg2" case in isMoveInstr
...
llvm-svn: 28945
2006-06-27 21:52:45 +00:00
4e76015e0b
lower more then 4 formal arguments. The offset is currently hard coded.
...
implement SelectFrameIndex
llvm-svn: 28751
2006-06-12 12:28:08 +00:00
6306becc49
add R0 to liveout
...
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch
llvm-svn: 28691
2006-06-05 22:26:14 +00:00
5bc60da112
Expand ret into "CopyToReg;BRIND"
...
llvm-svn: 28559
2006-05-30 17:33:19 +00:00
a3add0fea8
Change RET node to include signness information of the return values. i.e.
...
RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
4781610886
port the ARM backend to use ISD::CALL instead of LowerCallTo
...
llvm-svn: 28469
2006-05-25 11:00:18 +00:00
4af59dac0b
Assert if InflightSet is not cleared after instruction selecting a BB.
...
llvm-svn: 28459
2006-05-25 00:24:28 +00:00
1a8e74d113
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
...
non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
27f8bdc7e5
implement minimal versions of
...
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
llvm-svn: 28431
2006-05-23 02:48:20 +00:00
Bob Wilson